Memory Write Reliability Detection Without Verify
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Solution Overview
Problem
Memory devices face reliability risks and increased power consumption due to the omission of program verify operations, which are skipped to reduce write times and power usage, leading to potential incorrect data storage as cells degrade over time.
Innovation Solution
Implementing a mechanism to monitor ramping time during write operations, where a threshold is set to determine if a program verify operation is necessary, allowing for reduced power consumption and faster write times while maintaining reliability by performing verification only when the ramping time exceeds a predetermined threshold, indicative of potential reliability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If program verify operations are omitted to reduce write times and power consumption, then write speed and energy efficiency are improved, but data storage reliability deteriorates
Solution Approach 1:
The patent implements a feedback mechanism by monitoring ramping time during write operations and using this information to determine whether verification is necessary. The system measures the actual ramping time, compares it against a threshold, and adjusts verification behavior accordingly - performing verification only when ramping time exceeds the threshold, thus maintaining reliability while improving write speed.
Solution Approach 2:
The patent changes the parameter of verification frequency based on the measured ramping time parameter. Instead of always performing verification or never performing verification, the system dynamically adjusts verification execution based on the ramping time parameter, performing verification selectively when the parameter indicates potential reliability issues.
2Reliability
If program verify operations are performed with every write, then data storage reliability is improved, but power consumption and write time increase
Solution Approach 1:
The system uses feedback from ramping time measurement to control verification execution. By monitoring the ramping time and comparing it to a threshold, the system determines whether verification is needed, performing verification only when necessary rather than unconditionally, thus reducing power consumption while maintaining reliability.
Solution Approach 2:
Instead of performing verification in all cases (excessive action) or no cases (insufficient action), the patent applies partial action by performing verification only in specific conditions where ramping time exceeds the threshold. This selective approach optimizes power consumption while maintaining adequate reliability.
3Productivity
If program verify operations are skipped to reduce write times, then write speed is improved, but the risk of incorrect data storage increases
Solution Approach 1:
The patent employs feedback control by measuring ramping time during the write operation and using this measurement to determine whether verification should be performed. This feedback mechanism allows the system to maintain high write speeds by skipping verification when ramping time is within acceptable ranges while performing verification when ramping time indicates potential issues.
Solution Approach 2:
The system performs preliminary measurement of ramping time before deciding whether to execute verification. This preliminary action provides information that guides the subsequent verification decision, enabling the system to prepare for potential verification needs while maintaining efficient write operations.
Data Source
AI summary
Implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. In some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. The memory device may set a flag value based on comparing a transition time and a transition time threshold. The transition time may be a time to transition from a first voltage to a second voltage during the program operation. The memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.