Memory Controller Write Reordering for Sequential NAND Writes
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Solution Overview
Problem
Non-volatile memory modules require commands from a host system to perform data operations, but existing technologies fail to provide commands from a host system to perform data operations, leading to decreased performance due to random write operations caused by multi-threading.
Innovation Solution
A data writing method and memory controller that reorder write instructions to ensure sequential execution, using a buffer memory to store instructions with sequential marks and logical addresses, and a processor to rearrange instructions for sequential write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multi-threading technology is used to improve host system performance, then processing speed is improved, but write operations become random rather than sequential, causing storage device performance to decrease
Solution Approach 1:
The patent introduces a memory controller as an intermediary between the host system and non-volatile memory module. The memory controller receives write commands from multiple host threads, reorders them into sequential order, and then transmits them to the memory module. This intermediary component resolves the contradiction by allowing the host to use multi-threading for parallel command submission while ensuring sequential execution at the storage device, thus maintaining both high processing speed and optimal write performance.
2Adaptability or versatility
If write commands are executed randomly by multiple processing threads, then parallel processing capability is improved, but sequential write performance deteriorates
Solution Approach 1:
The patent segments the write command processing into two distinct phases: command reception and command execution. Multiple host threads can simultaneously submit write commands during the reception phase, demonstrating parallel processing capability. The memory controller then segments and reorders these commands during the execution phase to ensure sequential processing. This segmentation allows the system to maintain both parallel processing versatility and sequential write reliability.
3Productivity
If multiple threads send write instructions simultaneously, then throughput is improved, but write order becomes disordered, reducing data access capability
Solution Approach 1:
The memory controller implements a feedback mechanism by monitoring the arrival order of write commands from multiple threads and using this information to reconstruct the correct sequential order. The controller tracks command identifiers and uses feedback loops to reorder commands before transmission to the memory module. This feedback-based reordering allows the system to accept high-volume simultaneous write submissions while maintaining precise control over the final execution sequence, thus preserving both throughput and write order accuracy.
Data Source
AI summary
A memory controller and data writing method are provided. The data writing method includes: obtaining and storing a first instruction sequence comprising a plurality of write instructions to a buffer memory; determining a plurality of first write instructions that satisfy preset conditions according to first information and second information of the write instructions; performing ascending order arrangement on the plurality of first write instructions to form a second instruction sequence; according to the second instruction sequence, sequentially executing each first write instruction so as to write sequential write data into a rewritable non-volatile memory module. As such, the write data corresponding to sequential write instructions can be effectively written sequentially into the rewritable non-volatile memory module, so as to actually execute sequential write operation required by a host system, thereby reducing random write operations caused by multi-threading and improving overall data access capability of a storage device.