Semiconductor Memory Write Strategy Using Segmented Verification
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently writing data to memory cell transistors, particularly in reducing the width of threshold voltage distributions and optimizing write operations to prevent overlapping of threshold voltage levels, which affects data retention and storage efficiency.
Innovation Solution
The semiconductor memory device employs a write operation strategy involving multiple loops of program operations with verification steps, adjusting voltages and program verification operations to classify memory cell transistors into groups, allowing for targeted programming and reducing the number of verification operations, thereby optimizing the write process and maintaining threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple verification operations are performed during write operations to ensure accurate data storage, then data retention reliability is improved, but write operation time increases
Solution Approach 1:
The patent segments memory cell transistors into multiple groups based on their threshold voltage characteristics. By dividing the memory cells into groups (first group with lower threshold voltage, second group with higher threshold voltage), the patent can apply different verification strategies to different groups, reducing the overall verification time while maintaining data reliability for each segment.
Solution Approach 2:
The patent applies different verification operations to different groups of memory cells based on their local characteristics. The first group requires verification operations to ensure data retention, while the second group does not require verification. This local differentiation optimizes the balance between reliability and write speed by tailoring verification requirements to each group's threshold voltage profile.
2Quantity of substance
If program operations are performed to write data to memory cell transistors, then data storage capacity is improved, but threshold voltage distribution width increases causing overlap
Solution Approach 1:
The patent divides memory cell transistors into distinct groups based on threshold voltage ranges. The first group has threshold voltages below a first reference level, while the second group has threshold voltages above a second reference level. This segmentation prevents threshold voltage distribution overlap by creating clear separation between groups, enabling reliable multi-level cell (MLC) or triple-level cell (TLC) storage without interference between adjacent voltage distributions.
Solution Approach 2:
The patent changes the threshold voltage parameter of memory cell transistors through controlled program operations. By adjusting programming conditions and applying specific voltages to word lines and bit lines, the patent can precisely control the threshold voltage shift, ensuring that distributed threshold voltages remain within desired ranges and do not overlap between different data states or memory cell groups.
3Productivity
If verification operations are reduced to increase write speed, then productivity is improved, but measurement precision of threshold voltage classification deteriorates
Solution Approach 1:
The patent performs preliminary classification of memory cell transistors into groups based on their threshold voltage characteristics before executing the full write operation. By pre-identifying which memory cells belong to the first group (requiring verification) and which belong to the second group (not requiring verification), the patent can streamline subsequent operations and avoid unnecessary verification steps, thereby improving write speed while maintaining classification accuracy.
Data Source
AI summary
A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.