Semiconductor Memory Write Sequence Optimization
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in the write operation due to variations in writing characteristics across memory cells, leading to prolonged write times and potential reliability issues related to threshold voltage distribution spreading.
Innovation Solution
A semiconductor memory device with a control unit that performs a preliminary program operation and detection verify operation to correct the write sequence, adjusting the number of loops and verify operations based on detected writing characteristics, thereby optimizing the write process and reducing the spread of threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed write sequence with predetermined number of loops is used, then the write operation can be completed with a standard process, but the write time is prolonged due to variations in writing characteristics across memory cells
Solution Approach 1:
The patent performs a preliminary program operation before the main write sequence to detect writing characteristics of memory cells. Based on the detection results, the write sequence is corrected and optimized. This preliminary action enables subsequent write operations to be adjusted according to actual cell characteristics, reducing write time while maintaining reliability.
Solution Approach 2:
The patent implements a feedback mechanism where detection verify operations measure the writing characteristics of memory cells, and this measurement information is used to correct and optimize the write sequence. The control unit adjusts the number of loops and verify operations based on detected characteristics, creating a closed-loop control system that improves write speed while adapting to cell variations.
2Reliability
If the number of verify operations is increased to ensure reliability, then threshold voltage distribution spreading is reduced, but write time is prolonged
Solution Approach 1:
The patent applies partial verify operations selectively based on detected writing characteristics. Instead of uniformly applying the maximum number of verify operations to all memory cells, the system performs verify operations only to the extent necessary for each cell's characteristics. This partial action approach maintains reliability by ensuring adequate verification while avoiding excessive verify operations that would prolong write time unnecessarily.
Solution Approach 2:
The patent dynamically adjusts the number of verify operations and loop iterations based on real-time detection of writing characteristics. The write sequence is not fixed but adapts to the actual performance of each memory cell, allowing the system to optimize the balance between reliability and write time for each specific cell rather than using a static, one-size-fits-all approach.
3Productivity
If a standard write sequence is used for all memory cells, then the control process is simplified, but writing characteristics variations lead to inefficiencies and potential reliability issues
Solution Approach 1:
The patent applies local quality by tailoring the write sequence to the specific writing characteristics of each memory cell or cell group. Instead of using a uniform write sequence for all cells, the system detects individual cell characteristics and applies customized write parameters (number of loops, verify operations, voltages) to each cell's local requirements. This localized approach improves write operation efficiency by matching the write process to actual cell performance while the control unit manages the complexity of individualized sequences.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a memory cell array having plural memory cells that can be set to any one of plural different threshold voltages, plural bit lines connected to the plural memory cells respectively, a word line connected to gates of the plural memory cells, a control unit configured to execute a write sequence for repetitively performing plural loops including a set of a program operation of writing data into the memory cells and a verify operation of verifying data written in the memory cells to write predetermined data in the memory cells MT, and prior to execution of the write sequence, the control unit corrects the write sequence based on a result of performing the preliminary program operation and the detection verify operation on the memory cells.