Semiconductor Memory Write Suspension and Resume Verification

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Solution Overview

Problem

Semiconductor memory devices face challenges in reliably suspending and resuming write operations without causing miswriting due to over-programming, especially when data retention leads to threshold voltage decreases during suspension.

Innovation Solution

The semiconductor memory device implements a write operation that suspends and resumes with adjusted target levels and sense periods for verify operations, setting a lower target level for the first verify operation after resumption to reduce miswriting and over-programming, and applies different program conditions based on previous verify results.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the write operation is suspended and resumed with standard verify parameters, then the write operation can be interrupted for external access, but miswriting and over-programming occur due to threshold voltage decreases from data retention

Engineering Contradiction:
Improvewrite operation suspension capabilityVSAvoiddata writing accuracy
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent changes the verify operation parameters (target level and sense period) based on whether a write operation was suspended. When resuming after suspension, the target level is set lower and the sense period is extended compared to normal operations. This parameter adaptation resolves the contradiction by allowing suspension capability while preventing miswriting through adjusted verification criteria that account for threshold voltage drift during suspension.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the sense period is extended to detect threshold voltage changes, then detection accuracy improves, but operation time increases

Engineering Contradiction:
Improvethreshold voltage detection accuracyVSAvoidverify operation duration
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent dynamically adjusts the sense period duration based on the operational context. A longer sense period is used only when resuming after suspension to detect threshold voltage changes, while normal operations use a shorter sense period. This dynamic adjustment resolves the contradiction by extending detection time only when necessary, improving accuracy without consistently increasing operation time.

Inventive Principle:
Principle #15Dynamics

3Manufacturing precision

If the target level is lowered to prevent over-programming, then writing accuracy improves, but programming completeness may be compromised

Engineering Contradiction:
Improveprogramming precisionVSAvoiddata retention completeness
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent uses feedback from the sense operation results to determine whether to continue programming or switch to read-only mode. The lowered target level provides a safety margin that prevents over-programming, while the feedback mechanism ensures that programming is completed sufficiently by verifying whether cells have reached an adequate threshold voltage state before stopping, thus resolving the contradiction between precision and completeness.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10249377B2Semiconductor memory device
Publication Date: 2019.04.02 KIOXIA CORP
  • US10249377B2 patent drawing
  • US10249377B2 patent drawing
  • US10249377B2 patent drawing

AI summary

According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, a sense amplifier, a word line, and a row decoder. A write operation repeats a program loop including a program operation, first and second verify operations. The row decoder applies a first read voltage to the word line in the first and second verify operations. When the write operation is not suspended, the sense amplifier senses a voltage of the bit line for a first sense period in the first verify operation. When the write operation is suspended, the sense amplifier senses the voltage of the bit line for a second sense period shorter than the first sense period in the initial first verify operation after a resumption of the write operation.