Memory IC On-Die Termination Sequencing for Write Signal Matching
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Solution Overview
Problem
High-speed signaling systems with single on-die termination schemes experience sub-optimal performance due to impedance discontinuity and signal attenuation, leading to reduced signaling margins and increased error rates.
Innovation Solution
Implementing multiple, graduated on-die termination structures per high-speed signaling line, allowing for switchable selection between high-load (hard) and low-load (soft) terminations within memory devices, enabling optimized load-matching and reflection cancellation without undue signal attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single on-die termination structure is used, then device complexity is reduced, but signaling margins deteriorate due to impedance discontinuity and signal attenuation
Solution Approach 1:
The patent divides the termination structure into multiple segmented elements (first termination element and second termination element) that can be independently controlled. Each element can be selectively enabled or disabled based on operational mode, allowing the system to optimize between hard termination (both elements enabled) and soft termination (one element enabled) configurations, thereby improving signaling margins without excessive complexity
Solution Approach 2:
The patent implements dynamic control of termination structures through mode signals that enable or disable specific termination elements based on operational requirements. The termination configuration changes dynamically between hard and soft termination modes, allowing the system to adapt to different signaling conditions and optimize performance for both destination and non-destination memory modules
2Reliability
If hard termination is applied to non-destination module, then reflection cancellation is improved, but signal attenuation increases if applied to destination module
Solution Approach 1:
The patent applies different termination qualities to different operational contexts by selectively enabling termination elements based on whether the memory module is the destination or non-destination. Destination modules receive soft termination (lower attenuation) while non-destination modules receive hard termination (better reflection cancellation), optimizing performance for each local condition
Solution Approach 2:
The patent changes the termination parameter (impedance matching strength) based on operational mode. The mode signal controls whether termination elements are enabled or disabled, effectively changing the termination impedance parameter from hard termination values to soft termination values depending on whether the module is the destination, thereby adapting to different signal transmission requirements
3Reliability
If on-die termination is enabled, then impedance matching is improved, but signal attenuation increases
Solution Approach 1:
The patent dynamically adjusts the termination configuration by enabling or disabling specific termination elements based on operational mode. The system transitions between hard termination (stronger impedance matching but higher attenuation) and soft termination (weaker impedance matching but lower attenuation) to optimize the balance between impedance matching and signal attenuation for each operational context
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signaling margins, reduces bit error rates, and provides additional headroom for increased signaling rates by dynamically adjusting terminations based on the destination memory module.
Implementation Method 1
High-speed signal lines are commonly terminated by resistive loads selected to match the characteristic impedance of the signal lines and thereby cancel undesired reflections
Data Source
AI summary
A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.