Memory Write Timing Adjustment Using Error Detection Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory devices with synchronous interfaces, variations such as temperature and jitter cause attenuation in data and clock signals, leading to poor data recovery, especially as operating frequencies increase, necessitating adjustments in write timing to ensure proper sampling.
Innovation Solution
A method and system that adjust the write timing in memory devices by determining a write timing window based on error detection results, allowing for phase adjustments between data bus signals and write clock signals to optimize data recovery, involving error detection functions and phase delay circuits to synchronize data and clock signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating frequency is increased to transmit data more rapidly, then the data transmission speed is improved, but the data signal integrity deteriorates due to attenuation and timing errors
Solution Approach 1:
The patent implements a feedback mechanism where the memory device performs error detection on received data patterns and transmits error detection results back to the processing unit. The processing unit then adjusts the write timing based on these results, creating a closed-loop system that continuously optimizes data transmission reliability at high frequencies.
Solution Approach 2:
The patent dynamically changes the write timing parameter (phase difference between data signal and clock signal) based on error detection results. By adjusting the write timing window and phase offset, the system optimizes signal sampling accuracy to maintain data integrity despite increased transmission frequency and associated attenuation.
2Reliability
If the write timing is adjusted to improve data recovery accuracy, then the data integrity is improved, but the system complexity increases due to additional error detection and timing adjustment mechanisms
Solution Approach 1:
The patent integrates error detection functionality into the existing memory device architecture, allowing the same hardware to serve both its primary data storage function and the additional error detection function. The error detection unit operates within the memory device's existing data path, and the timing adjustment mechanism leverages the existing clock and data signal infrastructure, thereby minimizing additional complexity while achieving improved data recovery accuracy.
Data Source
AI summary
A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.