Semiconductor Memory Write Timing Separation
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Solution Overview
Problem
The increasing bit errors in semiconductor memory devices due to the scaling down of manufacturing processes in DRAMs necessitate improved integrity and performance, particularly in separating the write timings of data and parity data to enhance operational efficiency.
Innovation Solution
A semiconductor memory device incorporating a memory cell array with both data and parity regions, an error correction code (ECC) engine, and a control logic circuit that adjusts the write timing of parity data based on command timings, allowing for background generation of parity data without affecting write data operations, thereby separating their write timings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the manufacturing process is scaled down to increase yield, then productivity is improved, but bit errors in memory cells increase
Solution Approach 1:
The patent divides the memory cell array into a data region and a parity region. The data region stores write data while the parity region stores parity data generated from the write data. This segmentation allows independent management of data and error correction information, enabling the system to handle increased bit errors resulting from manufacturing scaling by providing dedicated error correction capability through the parity region.
2Reliability
If parity data is generated and written simultaneously with write data, then reliability is improved, but write speed decreases
Solution Approach 1:
The control logic circuit generates parity data in advance during a background operation before the write data is actually written to the memory cell array. The parity data is stored in a buffer and ready when needed. This preliminary generation of parity data allows the write operation to proceed at full speed without waiting for parity calculation, while still ensuring data integrity through the pre-prepared error correction information.
Solution Approach 2:
The patent enables continuous background operation for parity data generation that does not interrupt the main write data operation. The control logic circuit continuously generates parity data for incoming write data in the background, allowing both operations to proceed concurrently. This continuity ensures that error correction capability is maintained without compromising write speed, as the parity generation happens in parallel with the write operation.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a data region and a parity region. The I/O gating circuit is connected to the ECC engine and the memory cell array. The control logic circuit generates control signals by decoding a command received from a memory controller. The ECC engine is configured to a first parity data based on a first write data associated with a first command. The control logic circuit is further configured to adjust a first write timing to write the first parity data in the parity region based on a receiving timing of a second command successive to the first command and a reference time interval.