Memory Write Validation Using Pre-Computed Error Detection Codes

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Solution Overview

Problem

Current mechanisms for writing data to memory, such as DRAM, do not adequately verify the correctness of data after it is written, leading to potential corruption and reliability issues.

Innovation Solution

A device comprising a receiving unit, a validation unit, and an alert unit that receives data and a first error detection code, validates the data by comparing it with a second error detection code generated after writing, and generates an alert if the data is incorrect, allowing for write checking and retry without resending the data to the controller.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is written to memory without post-write verification, then writing speed is improved, but data reliability deteriorates

Engineering Contradiction:
Improvedata writing speedVSAvoiddata correctness
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by generating the second error detection code in advance (before the write operation completes) and storing it in the memory device alongside the data. This allows the memory device itself to perform verification without waiting for controller resending, thus maintaining writing speed while ensuring data reliability through pre-prepared verification capability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements self-service by enabling the memory device to autonomously verify written data using the stored second error detection code, without requiring the controller to resend data for verification. The memory device independently detects write errors and generates alerts, making the system self- verifying and eliminating the need for external verification cycles.

Inventive Principle:
Principle #25Self-service

2Reliability

If data is resent to controller for verification, then data reliability is improved, but communication overhead increases

Engineering Contradiction:
Improvedata verification accuracyVSAvoidcommunication protocol complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the verification function from the controller and relocates it to the memory device. By generating and storing the second error detection code within the memory device and enabling autonomous verification, the patent removes the need for complex resending and verification communication protocols between controller and memory, simplifying the overall system while maintaining verification capability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If error detection codes are generated and compared, then data integrity is improved, but processing time increases

Engineering Contradiction:
Improvedata integrity verificationVSAvoidverification processing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by generating the second error detection code before the write operation completes and storing it in the memory device. This pre-computation approach ensures that when verification is needed, the comparison can be performed immediately without additional processing delay, thus maintaining data integrity verification while minimizing time loss.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10078541B2Validate written data
Publication Date: 2018.09.18 HEWLETT PACKARD ENTERPRISE DEV LP
  • US10078541B2 patent drawing
  • US10078541B2 patent drawing
  • US10078541B2 patent drawing

AI summary

Data and a first error detection code related to the data is received. That the received data is written correctly to a memory is validated based on the first error detection code and/or a comparison of the written data to the received data. An alert is generated if it is determined that the written data is incorrect.