Nonvolatile Memory Write Speed via Adjacent Cell Voltage Control
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Solution Overview
Problem
The existing nonvolatile semiconductor memory devices with stacked memory cells face challenges in data retention due to unwanted charge movement between adjacent memory cells with different threshold voltages, leading to degradation of data retention characteristics.
Innovation Solution
A nonvolatile semiconductor memory device is designed with a control circuit that applies the same program voltage to adjacent memory cell groups, preventing unwanted charge movement by ensuring all non-write cells are raised to a positive threshold voltage, thereby eliminating the need for writing back the erase level to positive, which speeds up the data write process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If different program voltages are applied to adjacent memory cell groups to write data selectively, then data write capability is improved, but unwanted charge movement occurs between adjacent cells causing data retention degradation
Solution Approach 1:
The patent applies preliminary anti-action by raising the threshold voltage of non-write memory cells to a positive level before data write operations. This preemptive action creates a protective potential barrier that prevents unwanted charge movement from write cells to adjacent non-write cells, thereby eliminating data retention degradation while maintaining selective data write capability.
Solution Approach 2:
The patent implements equipotentiality by applying the same program voltage to both write and adjacent non-write memory cells simultaneously. This equalizes the electrical potential conditions across adjacent cells, preventing charge leakage from high-threshold write cells to low-threshold non-write cells, thus resolving the data retention issue while preserving write functionality.
2Reliability
If all adjacent memory cell groups are raised to positive threshold voltage to prevent charge movement, then data retention reliability is improved, but the number of write pulses increases prolonging write time
Solution Approach 1:
The patent applies local quality by selectively raising the threshold voltage to positive levels only in specific non-write memory cell groups adjacent to write cells, rather than uniformly across the entire memory array. This localized approach prevents charge movement at critical interfaces while minimizing the scope of voltage application, thereby reducing the number of write pulses required and shortening write time.
Solution Approach 2:
The patent segments the memory cell array into distinct write and non-write regions, applying different voltage strategies to each segment. Write cells receive selective program voltages for data writing, while adjacent non-write cells receive elevated voltages only when needed for charge prevention. This segmentation allows parallel processing of write operations without requiring all cells to undergo the same write pulse sequence, thus reducing overall write time.
3Speed
If selective write voltage is applied only to target memory cells, then write speed is improved, but charge leakage occurs to adjacent cells with lower threshold voltage
Solution Approach 1:
The patent implements preliminary action by pre-raising the threshold voltage of adjacent non-write memory cells to a positive level before applying write voltages to target cells. This preparatory step establishes a protective potential barrier in advance, preventing charge leakage during subsequent write operations without requiring additional write pulses, thus maintaining high write speed while eliminating charge leakage.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array having a plurality of memory cells is connected to a plurality of word lines stacked on a semiconductor substrate, and the memory cells having a charge accumulation layer, and the charge accumulation layers are united between adjacent memory cells. When writing data to a memory cell group connected to the nth (n is a natural number) word line of the memory cell array, the control circuit controls to simultaneously apply the same program voltage to memory cell groups connected to the (n−1)th and (n+1)th word lines.