Memory Cell Group Write Voltage Layout for Lower Program Variation
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in suppressing program variation in memory cells, which can affect data integrity and reliability.
Innovation Solution
The semiconductor memory device employs a configuration with multiple memory cell groups and sense amplifier groups that supply different voltages to bit lines during write operations, thereby reducing program variation by optimizing voltage distribution across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single sense amplifier supplies voltage to all bit lines, then device complexity is reduced, but program variation increases
Solution Approach 1:
The sense amplifier module is divided into multiple sense amplifier groups (first sense amplifier group and second sense amplifier group), where each group supplies voltage to specific bit lines. This segmentation allows different voltage levels to be supplied to different memory cell groups, reducing program variation while maintaining manageable device complexity through modular organization.
Solution Approach 2:
Different sense amplifier groups supply different voltages to different bit lines connected to specific memory cell groups. This local quality approach ensures that each memory cell group receives the optimal voltage for its specific characteristics, thereby reducing program variation and improving write reliability without requiring complete redesign of the entire system.
2Reliability
If multiple sense amplifier groups supply different voltages to bit lines, then program variation is reduced, but device complexity increases
Solution Approach 1:
Multiple sense amplifier groups are designed with identical circuit structures and functionalities, where each group can independently supply voltage to its assigned bit lines. This universality allows the system to achieve reduced program variation through voltage differentiation while maintaining design simplicity and ease of manufacturing, as the same modular unit is replicated across different groups.
Data Source
AI summary
A semiconductor memory device includes a first to eighth memory cell groups arranged along a first direction, a first word line extending in the first direction and a first to an eighth sense amplifier groups configured to be capable of supplying voltages to the first to the eighth memory cell groups, respectively. Each of the first to the eighth memory cell groups includes a plurality of memory cells and a plurality of bit lines each connected to the plurality of memory cells. In a write operation of supplying a program voltage to the first word line, the first sense amplifier group supplies a first voltage to the bit line connected to a write target memory cell of the first memory cell group, and the second sense amplifier group supplies a second voltage to the bit line connected to a write target memory cell of the second memory cell group.