Nonvolatile Memory Write Voltage Mode Selection
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Solution Overview
Problem
The increasing complexity of multi-level data storage in flash memories leads to longer write times due to the need for finer control over threshold voltage differences, which existing techniques have not adequately addressed while maintaining reliability.
Innovation Solution
A nonvolatile semiconductor memory system that includes a memory cell array, row and column control circuits, a latch circuit, and a processing unit to scan and determine the appropriate write mode based on the number of to-be-written memory cells, allowing for efficient data writing by calculating a first write voltage during lower-data writing and setting a second write voltage based on setting information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level data storage is implemented in flash memory, then memory capacity is increased, but write time becomes longer due to finer control requirements
Solution Approach 1:
The patent applies dynamics by making the write voltage application strategy adaptive rather than fixed. The control circuit dynamically selects between single-pass and multi-pass write operations based on the actual data pattern being written. When data allows, single-pass writing is used to minimize write time; when data requires finer control, multi-pass writing is automatically selected, thus adapting the write process to the specific conditions.
Solution Approach 2:
The patent changes the parameter of write voltage application by switching between different write modes (single-pass vs. multi-pass) based on data characteristics. The control circuit analyzes the data pattern and adjusts the write operation parameters accordingly, selecting the appropriate number of passes and voltage levels to optimize both write speed and reliability for each specific data set.
2Manufacturing precision
If the number of write voltage applications is increased for multi-level data, then data accuracy is improved, but write operation time increases
Solution Approach 1:
The patent applies partial action by performing write operations in variable passes rather than always using full multi-pass sequences. The control circuit determines the minimum necessary passes based on data characteristics, applying write voltage only as many times as needed to achieve the required threshold voltage precision. This avoids unnecessary repeated write operations that would waste time while still ensuring adequate precision control.
Solution Approach 2:
The patent implements feedback through the control circuit that monitors data patterns and adjusts the write operation strategy accordingly. The control circuit receives information about the data to be written, analyzes whether single-pass or multi-pass writing is appropriate, and automatically selects the optimal approach. This feedback mechanism ensures that write precision requirements are met without unnecessarily increasing write time.
3Productivity
If write voltage is calculated during lower-data writing, then upper-data writing efficiency is improved, but control circuit complexity increases
Solution Approach 1:
The patent applies preliminary action by calculating and preparing the write voltage for upper-data writing during the lower-data writing phase. The control circuit uses the lower-data write operation as an opportunity to pre-compute the appropriate voltage parameters for the subsequent upper-data write, so that when upper-data writing begins, the voltage settings are already optimized and ready to apply, reducing overall write time.
Solution Approach 2:
The control circuit is designed with multi-functionality to perform both lower-data and upper-data write operations while also conducting voltage calculations during the lower-data phase. This universal control circuit can adapt its behavior based on the current write phase, serving multiple purposes: executing lower-data writes, calculating upper-data voltages, and then executing upper-data writes, thereby reducing the need for separate dedicated circuits.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory includes memory cells storing data of multi-level, a bit scan circuit to scan the number of to-be-written memory cells and the number of memory cells that have passed the verify, a processing unit to perform an operation process based on a scan result of the bit scan circuit, and a control circuit to control an operation of writing data according to a first mode in which a voltage used for an upper-data writing is calculated during a lower-data writing and a second mode used a voltage based on setting information. The bit scan circuit scans the number of to-be-written memory cells before starting writing and the processing unit compares the number of to-be-written memory cells with a criterion and determines one of the first and second modes for the writing based on a result of comparison.