Memory Write Voltage Reduction via Bit-Line Pre-Discharge
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Solution Overview
Problem
Current methods for reducing write minimum supply voltage (WVmin) in memory cells either increase the size and power consumption of memory arrays or have limited voltage droop due to retention issues in unselected cells, making it challenging to achieve lower power dissipation while maintaining performance.
Innovation Solution
The implementation of a power device that provides a weak connection between the core power supply and the bit-cell supply, allowing for a self-induced collapse of the power supply voltage (CVcc) through pre-discharging write bit-lines and using stronger pull-up devices, which enables a higher voltage droop without affecting unselected cells' retention margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of write-access/pull-up devices is increased to reduce WVmin, then the write minimum supply voltage is reduced, but the overall size of the memory arrays increases
Solution Approach 1:
The patent applies preliminary action by pre-discharging the write bit-lines before the actual write operation. This pre-conditioning of the bit-lines enables the memory cell to achieve the required voltage droop for successful write at lower supply voltages without needing larger transistors, thus resolving the contradiction between reducing WVmin and maintaining compact memory array size
Solution Approach 2:
The patent changes the temporal parameters of the write operation by introducing a delayed write scheme where the word-line is activated before the bit-lines are fully charged. This parameter change in timing sequences allows the memory cell to experience optimal voltage conditions for write operations at reduced supply voltages, achieving lower WVmin without increasing device size
2Reliability
If conventional write assist techniques are used to reduce WVmin, then the write operation can proceed at lower voltages, but the voltage droop is limited due to retention issues in unselected cells
Solution Approach 1:
The patent applies segmentation by dividing the memory array into selected and unselected regions, and by separating the write operation into distinct phases. The write bit-lines are pre-discharged only for selected cells while unselected cells maintain their retention conditions. This segmentation allows independent optimization of write voltage droop for selected cells without compromising unselected cell retention, thereby achieving greater voltage droop with better control
Solution Approach 2:
The patent uses preliminary action by pre-discharging the write bit-lines before activating the word-line for selected memory cells. This preliminary conditioning creates the necessary voltage differential for write operations at lower supply voltages. The pre-discharge is selectively applied only to bit-lines associated with selected cells, allowing controlled voltage droop without affecting unselected cell retention margins
Data Source
AI summary
Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.