Semiconductor Memory Error Correction via Internal XOR Logic
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in performing error correction at high speeds due to the time-consuming process of data inversion and error identification, often resulting in erroneous data storage.
Innovation Solution
A semiconductor memory system with a read circuit, data latches, a computing unit, and a selector that performs arithmetic processing for error correction, allowing for rapid identification and correction of errors without the need for external logic circuits, and utilizing EXOR operations for bit inversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed using conventional read-write operations with external logic circuits, then error correction capability is achieved, but correction speed is slow and time consumption is high
Solution Approach 1:
The patent merges the error correction function into the memory device itself by integrating a computing unit within the memory architecture. This combines the storage function with the correction function, eliminating the need for separate external logic circuits and enabling faster correction operations to be performed directly within the memory device.
Solution Approach 2:
The patent implements preliminary action by preparing correction data in advance through the computing unit. The correction data is generated and stored in a dedicated latch before being needed, so that when an error occurs, the correction can be applied immediately without waiting for external processing, thus improving correction speed.
2Measurement precision
If data is read and written back through external logic circuits for error correction, then error identification is achieved, but the process takes much time
Solution Approach 1:
The patent extracts the error correction function from external logic circuits and places it directly within the memory device. This extraction allows the correction process to occur internally without the time delays associated with external data transfer and processing, significantly reducing correction time while maintaining accuracy.
Solution Approach 2:
The patent introduces an intermediary computing unit and correction data latch within the memory device that mediates between the stored data and the correction process. This intermediary structure enables rapid error identification and correction by providing a dedicated internal pathway for correction operations, eliminating the need for slow external processing.
3Reliability
If conventional read-write sequences are used for error correction, then data integrity is maintained, but the number of operation cycles increases
Solution Approach 1:
The patent merges multiple operation cycles into a single integrated correction operation by combining the correction logic and data storage within the same device. This merging reduces the number of separate read-write cycles needed and simplifies the overall operation sequence while maintaining data integrity through the dedicated correction mechanism.
Data Source
AI summary
In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects a result of the arithmetic processing to prepare write data. Thus, data obtained after performance of the arithmetic processing can be generated in a semiconductor memory by an operation performed immediately after data read. In addition, it is unnecessary to transfer data to an external logic circuit. Therefore, the result of the arithmetic processing can be written to a memory cell block in a subsequent clock.