Memory Output Buffer ZQ Calibration for Transistor Mismatch
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Solution Overview
Problem
Existing impedance calibration systems in memory sub-systems face inaccuracies due to transistor mismatches in ZQ calibration circuits, leading to incorrect impedance calibration codes, particularly when variations in transistor characteristics affect the resistance levels of pull-up and pull-down circuits.
Innovation Solution
Implementing a calibration unit with arrays of transistor sets, where each set includes multiple transistors, to generate ZQ calibration codes by averaging the values from two transistors, reducing the impact of individual transistor variations and ensuring robust and accurate coding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional ZQ calibration circuits use single transistors to generate calibration codes, then the circuit complexity is low, but the measurement precision of impedance calibration deteriorates due to transistor mismatches and variations
Solution Approach 1:
The patent combines multiple transistors (first and second transistors) into a single calibration unit to generate calibration codes. By merging the functionality of multiple transistors and averaging their values, the circuit achieves higher measurement precision while managing complexity through functional integration rather than simple parallel addition.
Solution Approach 2:
The patent changes the parameter approach by using multiple transistors with varying characteristics and averaging their values to generate calibration codes. This parameter diversification compensates for individual transistor variations and mismatches, improving impedance calibration accuracy without requiring perfectly matched single transistors.
2Reliability
If multiple transistors are used in calibration units to reduce variations, then the reliability of impedance calibration improves, but the device complexity increases
Solution Approach 1:
The patent segments the calibration function into multiple transistor units, where each transistor contributes to the overall calibration code. By dividing the calibration task across multiple transistors and averaging their individual values, the system achieves higher reliability through redundancy and error compensation while maintaining manageable complexity through modular segmentation.
Solution Approach 2:
The patent implements a feedback mechanism where the calibration codes generated by multiple transistors are averaged and used to adjust the impedance calibration. This feedback loop continuously refines the calibration accuracy by compensating for transistor variations, improving reliability while the automated feedback process manages the complexity of having multiple transistors.
Data Source
AI summary
Control logic in a memory device initiates an impedance (ZQ) calibration to be performed by a calibration circuit coupled to an output buffer of an input/output circuit the I/O circuit of the memory device. A first set of calibration units of the calibration circuit includes a first calibration unit and a second calibration unit, where a first calibration code including a first sequence of bit values is generated having at least one bit value of the first sequence generated by a first transistor set of the first calibration unit and a second transistor set of the second calibration unit. The first calibration code is provided to one or more pull-up units of the output buffer, where the first calibration code is used to calibrate a first impedance of the one or more pull-up units. A second calibration code including a second sequence of bit values is generated by a second set of calibration units and a third set of calibration units. The second calibration code is provided to one or more pull-down units of the output buffer to calibrate a second impedance of the one or more pull-down units.