Memristive Device Gate Terminal Drift Correction
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Solution Overview
Problem
Phase-change memory (PCM) technologies face reliability issues due to thermal disturbance and resistance drift, which cause decoding errors in multilevel-cell storage by altering the state of cells and increasing resistivity over time, respectively.
Innovation Solution
A memristor memory device with a gate terminal electrically isolated from the memristive memory cell is used to receive electrical signals for volatile modulation, incorporating temperature and resistance drift compensation units to correct non-ideal conductance modulations, thereby addressing thermal disturbance and resistance drift effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If phase-change memory is used for multilevel-cell storage to increase capacity and reduce cost-per-bit, then storage capacity and cost-effectiveness are improved, but reliability deteriorates due to thermal disturbance and resistance drift causing decoding errors
Solution Approach 1:
A gate terminal is introduced as an intermediary element that is electrically isolated from but adjacent to the memristive memory cell. This gate terminal receives electrical signals to provide volatile modulation of the cell's conductance, serving as a mediator to correct non-ideal conductance modulations caused by thermal disturbance and resistance drift, thereby maintaining reliability while preserving multilevel-cell storage capacity
Solution Approach 2:
The invention changes the operational parameters of the memristive memory cell by applying voltage signals to the gate terminal, which modulates the conductance of the cell in a controlled manner. This allows dynamic adjustment of the cell's electrical properties to compensate for drift effects and maintain accurate data representation across multiple storage levels
2Ease of manufacture
If thermal disturbance and resistance drift are present in PCM technology, then manufacturing simplicity is maintained, but measurement precision deteriorates due to altered cell states and increased resistivity over time
Solution Approach 1:
The gate terminal operates with a feedback mechanism where electrical signals are applied to the gate based on the desired conductance state, and the actual conductance is monitored through the input and output terminals. This feedback loop allows continuous correction of conductance deviations caused by thermal disturbance and resistance drift, maintaining measurement precision without complicating the manufacturing process
3Reliability
If a gate terminal electrically isolated from the memristive memory cell is added to correct non-ideal conductance modulations, then reliability is improved, but device complexity increases
Solution Approach 1:
The memory device is segmented into functionally distinct components: the memristive memory cell for data storage, the gate terminal for conductance modulation and correction, and the input/output terminals for signal transmission. This segmentation allows each component to perform its specific function independently, improving reliability through functional specialization while keeping the overall structure manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly enhances the reliability of PCM-based memory devices by reducing drift effects, ensuring accurate data storage and retrieval, and making PCM a viable technology for higher-volume manufacturing and future computing systems.
Implementation Method 1
The gate terminal may be configured for receiving an electrical signal for a volatile modulation of a conductance of the memristive memory cell
Data Source
AI summary
A memristor memory device comprises a memristive memory cell, an input terminal, an output terminal, and a gate terminal. The input terminal and the output terminal are directly attached to the memristive memory cell, and the gate terminal is electrically isolated from the memristive memory cell. The gate terminal is configured for receiving an electrical signal for a volatile modulation of a conductance of the memristive memory cell, by which a correction of non-ideal conductance modulations of the memristor memory device is achieved.