Memristive Multi-Terminal Spiking Neuron for Neuromorphic Computing
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Solution Overview
Problem
Current neuromorphic computing systems face limitations in scalability and power consumption due to their reliance on CMOS-based architectures, which are inefficient for complex temporal spiking behavior and require large hardware and energy resources, making them unsuitable for applications in size and power-constrained systems like airborne or space-deployed systems.
Innovation Solution
A memristive multi-terminal spiking neuron device is developed, utilizing multiple terminals with non-volatile and volatile memristors, capacitors, and a common electrode to generate programmable electrical spiking outputs in response to input signals, enabling efficient cognitive computing tasks by dynamically modulating spiking behavior without the need for digital circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOS-based architectures are used for neuromorphic computing, then compatibility with digital infrastructure is improved, but power consumption and circuit area increase significantly
Solution Approach 1:
The patent replaces CMOS electronic circuitry with a memristive device that directly emulates neuronal spiking behavior through electrical properties. The memristive device uses voltage-dependent resistance changes to model neuronal integration and firing, eliminating the need for complex CMOS circuit implementations of integrate-and-fire mechanisms.
Solution Approach 2:
The patent changes the fundamental operating parameters from digital voltage levels in CMOS to continuous resistance states in memristors. The memristive device utilizes analog resistance values to encode synaptic weights and temporal spike patterns, enabling efficient representation of complex temporal spiking behavior through parameter variation rather than complex circuit logic.
2Adaptability or versatility
If CMOS-based architectures are used for neuromorphic computing, then compatibility with digital infrastructure is improved, but circuit area footprint increases
Solution Approach 1:
The patent replaces extensive CMOS circuitry with a single memristive device structure. The device uses physical memristance properties to perform functions that would require multiple CMOS components including integrators, comparators, and switches, dramatically reducing the area required per neuron implementation.
Solution Approach 2:
The patent merges multiple functional components (synapse, integrator, spike generator) into a single memristive device. The device simultaneously performs synaptic weight storage, temporal integration of incoming spikes, and spike output generation through its inherent voltage-current characteristics, eliminating the need for separate circuit blocks.
3Ease of manufacture
If simple spiking mechanisms are used in CMOS, then ease of implementation is improved, but capability to resolve complex temporal spiking behavior is reduced
Solution Approach 1:
The patent uses continuous resistance parameter changes in the memristive device to encode and process complex temporal patterns. The device naturally exhibits multiple stable resistance states and hysteresis effects that enable it to distinguish and respond to different spike timing patterns, frequencies, and sequences without requiring complex control logic.
Solution Approach 2:
The patent exploits the dynamic, time-dependent resistance characteristics of memristors to capture temporal spiking behavior. The device's resistance evolves continuously based on the history of applied voltages, enabling it to naturally implement temporal integration, short-term plasticity, and pattern recognition functions that are difficult to achieve with static CMOS circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient cognitive computing with reduced size, weight, and power consumption, allowing for complex information processing and decision-making in neuromorphic systems, overcoming the limitations of previous CMOS-based systems by integrating memristor-based logic and state storage on a single substrate.
Implementation Method 1
These approaches utilize the mechanism of spiking by capacitor discharge and recharge modulated by a dynamically coupled type of volatile memristance known as negative differential resistance (NDR).
Implementation Method 2
a memristive device comprising at least one each of non-volatile memristor, volatile memristor, and capacitor
Data Source
AI summary
A memristive multi-terminal spiking neuron apparatus, comprising a non-volatile memristor, wherein the non-volatile memristor has a resistance ratio between the high-resistance and low-resistance states exceeding 4 decades of magnitude, wherein the non-volatile memristor retains its resistance states for a time period exceeding 1 second, a volatile memristor, wherein the volatile memristor retains its low-resistance state for a time period of less than 10 nanoseconds, and a capacitor, wherein the volatile memristor is in parallel with the capacitor. A method of making a programmable electrical spiking output from a memristive multi-terminal spiking neuron, comprising providing one or more devices wherein each device comprises a non-volatile memristor, a volatile memristor, wherein the volatile memristor is in parallel with the capacitor, providing a first input spiking signal to a neuron device, providing a second input spiking signal, and creating a programmable spiking output signal which changes.