Memristive XOR Gate Circuit With Single-Cycle In-Memory Logic

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Solution Overview

Problem

Existing memristive logic gate circuits are unable to perform XOR operations in a single cycle, requiring at least two consecutive cycles of OR- and NAND-like operations.

Innovation Solution

A memristive logic gate circuit design comprising a first and second input memristive device connected in series between supply voltage terminals, with optional auxiliary memristive devices, utilizing bipolar switching characteristics and specific threshold voltage conditions to achieve single-cycle XOR operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If existing memristive logic gate circuits are used to perform XOR operations, then the operation can be completed, but it requires at least two consecutive cycles of OR- and NAND-like operations instead of a single cycle

Engineering Contradiction:

Improveoperation speedVSAvoidcircuit structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The circuit is segmented into distinct functional regions: input memristive devices (A, B), auxiliary memristive devices (C, D), and output memristive devices (E, F), each performing specific logical functions. This segmentation allows the XOR operation to be completed in a single cycle by distributing computational tasks across multiple dedicated components rather than using a sequential multi-cycle approach.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Auxiliary memristive devices C and D act as intermediary elements between the input devices A and B and the output devices E and F. These intermediary devices enable the single-cycle XOR operation by providing additional computational pathways and state storage capabilities that facilitate simultaneous multi-step logical operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If multiple consecutive cycles are used to perform XOR operations, then the logical function can be realized, but power consumption increases and operation time is extended

Engineering Contradiction:

Improvelogical operation accuracyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The circuit performs the complete XOR operation continuously in a single cycle without interruption or reset between steps. All logical operations (AND, OR, NOT combinations) occur simultaneously and continuously through the coordinated switching of input, auxiliary, and output memristive devices, eliminating the need for multiple discrete operational cycles and reducing total energy consumption.

Inventive Principle:

Principle #20Continuity of useful action

3Ease of operation

If multiple read/write operations are performed to implement XOR logic, then the operation can be completed, but the Von-Neumann bottleneck is exacerbated due to unnecessary data transfer

Engineering Contradiction:

Improveoperation simplicityVSAvoidenergy loss from data transfer

Core Design Contradiction:

Ease of operationVSLoss of energy

Solution Approach 1:

The circuit merges the computational logic and data storage functions into a single integrated structure using memristive devices for both input data representation and intermediate computational states. This merging eliminates the need for separate read/write operations and external data transfer, allowing the XOR operation to be performed entirely in-place within the memory array, thereby reducing energy loss from data movement.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables efficient single-cycle XOR operations with reduced power consumption and minimal read/write operations, utilizing memristive devices in crossbar memory arrays for in-memory computation.

Implementation Method 1

Any or all of the memristive devices A, B, C, D, F might have a bipolar switching characteristics

Methodology Applied

Scientific EffectBipolar switching:

Implementation Method 2

The input voltages are chosen in such a way to fulfill the condition Vx≥Vthon·(1+k2·RHRS/RLRS+k4) wherein k2 and k4 are technology dependent values

Methodology Applied

Scientific EffectThreshold voltage switching:

Data Source

PatentUS12499939B2Memristive logic gate circuit

Publication Date: 2025.12.16 VIENNA UNIVERSITY OF TECHNOLOGY

AI summary

Memristive logic gate circuit, comprising a first memristive device (1), representing a first input node A of the logic gate circuit, a second memristive device (2), representing a second input node B of the logic gate circuit, and a third memristive device (3), representing an output node F of the logic gate circuit, wherein the first memristive device (1) and the second memristive device (2) are connected in series between a positive supply voltage terminal Vx (7) and a negative supply voltage terminal −Vx (8), wherein a connection point (6) is formed between the first memristive device (1) and the second memristive device (2), and wherein the third memristive device (3) is provided between the connection point (6) and a Ground contact (9).