Memristor Array Grouping for Logic Indicator Generation
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Solution Overview
Problem
Memristor arrays face security vulnerabilities due to straightforward resistance level and logic level relationships, making them susceptible to hijacking, and they have limited storage density, which becomes a concern as circuit space becomes more valuable.
Innovation Solution
A system and method that combine memristors with different resistance levels to generate a greater number of resistance levels, increasing storage density and security by obfuscating the resistance level and logic level relationship, allowing for more logic levels to be represented and stored.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If memristors with straightforward resistance level and logic level relationships are used, then the device complexity is reduced and ease of operation is improved, but security is worsened due to susceptibility to hijacking
Solution Approach 1:
The patent applies parameter changes by mapping multiple resistance levels to logic levels in a non-direct manner. Specifically, it establishes that a first resistance level maps to a first logic level, a second resistance level maps to a second logic level, and a third resistance level also maps to the second logic level. This many-to-one mapping relationship changes the parameter interpretation rules, making it difficult for attackers to determine the correct logic level from resistance measurements alone, thereby enhancing security while maintaining operational simplicity through programmed mapping rules.
2Quantity of substance
If more resistance levels are generated to increase storage density, then the quantity of stored information is improved, but device complexity is worsened
Solution Approach 1:
The patent applies merging by combining multiple memristors in parallel configurations to generate additional resistance levels. By connecting memristors with different resistance characteristics in parallel, the system creates a composite resistance level that would be difficult to achieve with a single memristor. This merging approach increases storage density by expanding the number of distinguishable resistance levels without requiring proportionally more individual memristor devices, thus improving quantity while controlling device complexity through efficient resource utilization.
Data Source
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AI summary
A device for generating a representative logic indicator of grouped memristors is described. The device includes a memristor array. The memristor array includes a number of first memristors having a first set of logic indicators and a number of second memristors having a second set of logic indicators. The second set of logic indicators is different than the first set of logic indicators. Each first memristor is grouped with a corresponding second memristor during a memory read operation to generate a representative logic indicator.