Memristor With Asymmetrical Transistors and Diode
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Solution Overview
Problem
Conventional two-terminal EEPROM-type memristors face issues with over-erase and high-voltage readout operations, leading to unreliable synapses-related modeling and parasitic programming problems in cross-point array configurations, which are costly and complex to implement.
Innovation Solution
A two-terminal floating gate memristor design utilizing parallel-connected asymmetrical transistors and a diode, where the readout transistor performs low-voltage readout operations and the injection transistor facilitates high-voltage program/erase operations, with a shared floating gate structure and diode connected to the drain terminals to prevent over-erase and sneak currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional two-terminal EEPROM-type memristors are used for synapses-related modeling, then data storage capability is achieved, but over-erase and high-voltage readout operations occur leading to unreliable modeling
Solution Approach 1:
The patent segments the single transistor into two parallel asymmetrical transistors with different channel lengths. The first transistor has a longer channel length optimized for low-voltage readout operations, while the second transistor has a shorter channel length optimized for high-voltage program/erase operations. This segmentation allows each transistor to be specialized for its specific function, enabling reliable low-voltage readout while maintaining data storage capability.
Solution Approach 2:
The patent applies local quality by giving each transistor different channel length characteristics tailored to its specific function. The first transistor's longer channel provides higher resistance and better control for low-voltage readout, while the second transistor's shorter channel provides lower resistance for efficient high-voltage program/erase operations. This localized optimization of transistor properties resolves the contradiction between readout voltage requirements and modeling reliability.
2Reliability
If conventional two-terminal EEPROM-type memristors are used, then data storage is achieved, but over-erase occurs during high-voltage operations
Solution Approach 1:
The patent segments the programming function from the readout function by using two separate transistors. The second transistor with shorter channel length is specifically optimized for high-voltage program/erase operations, while the first transistor with longer channel length handles low-voltage readout. This segmentation prevents the over-erase effect by ensuring that high-voltage operations are controlled by a transistor designed for that purpose, isolating the readout path from harmful high-voltage effects.
Solution Approach 2:
The shared floating gate acts as an intermediary that couples the two transistors while allowing them to operate independently for their respective functions. The floating gate stores the charge representing the stored data bit, mediating between the program/erase operations of the second transistor and the readout operations of the first transistor. This intermediary structure enables the two transistors to work together without interfering with each other's optimized performance.
3Adaptability or versatility
If three-terminal EEPROM-type devices are used for neural networks, then programming capability is achieved, but fabrication complexity increases due to double-poly CMOS processes
Solution Approach 1:
The patent merges the functionality of two separate transistors into a single integrated structure with a shared floating gate. Both transistors share the same floating gate, which is formed as a single polysilicon structure, eliminating the need for separate gate formations that would require double-poly processes. This merging achieves the complex programming capability of three-terminal devices while maintaining the simpler single-poly fabrication process of conventional two-terminal devices.
Solution Approach 2:
The shared floating gate structure provides multi-functionality by serving as the control element for both the first transistor (readout) and the second transistor (program/erase). This universal floating gate structure enables the device to perform both readout and program/erase operations with different voltage requirements, achieving the versatility of three-terminal devices while maintaining two-terminal simplicity and single-poly manufacturability.
4Productivity
If conventional two-terminal memristors are used in cross-point arrays, then array integration is achieved, but sneak currents occur during readout operations
Solution Approach 1:
The patent segments the current path control by using the diode to create unidirectional current flow. The diode is connected between the drains of the two parallel transistors, allowing current to flow in only one direction during readout operations. This segmentation of current control prevents sneak currents from flowing through non-selected cells in the cross-point array, enabling reliable array integration without the sneak current problem that plagues conventional resistive memory arrays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables reliable low-voltage readout and high-voltage program/erase operations while preventing over-erase and sneak currents, overcoming the limitations of conventional approaches and allowing for low-cost single-poly semiconductor fabrication.
Implementation Method 1
the diode functions both as a current limiter that prevents over-erase during the high-voltage erase operations
Implementation Method 2
a shared (integral, single-piece) floating gate structure that stores a charge transferred to/from the injection transistor during program/erase operations
Implementation Method 3
a readout (first) transistor of the parallel asymmetrical transistors avoids read-disturb problems by way of being configured with a relatively long channel length
Implementation Method 4
Floating gate technology employs the various programming mechanisms (e.g., Fowler-Nordheim tunneling and hot carrier injection) and associated circuit features to adjust (i.e., program or erase) the charge stored on floating gates
Implementation Method 5
Floating gate technology employs the various programming mechanisms (e.g., Fowler-Nordheim tunneling and hot carrier injection)
Data Source
AI summary
A two-terminal, single-poly floating gate memristor includes parallel-connected, asymmetrical readout and injection transistors having a shared floating gate structure, and a diode connected to drain terminals of the asymmetrical transistors. The injection transistor is configured with relatively high source/drain-to-gate capacitances to facilitate EEPROM-type (floating gate) program/erase operations (e.g., hot carrier injection and band-to-band tunneling of holes), and the readout transistor is configured (e.g., using a threshold voltage implant) to facilitate low-voltage readout operations. The diode is configured to function both as a limiting resistor that prevents over-erase during high-voltage erase operations, and also to prevent sneak (leakage) currents during low-voltage readout operations. The diode is implemented using either p-n junction or Schottky diode configurations formed on bulk silicon, or a lateral diode configurations disclosed for SOI substrates. A memory circuit including multiple two-terminal memristors disposed in a cross-point array is disclosed, which can be utilized, e.g., in a neuromorphic circuit.