Memristor Array Calibration for Analog Computation Accuracy
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Solution Overview
Problem
Existing memory computing integrated devices based on memristors face challenges in achieving accurate and reliable calculations due to errors and fluctuations caused by natural randomness, non-ideal characteristics, and environmental deviations, which affect the accuracy of the calculation results.
Innovation Solution
The proposed calibration method involves a middle-level and medium-grained approach for intermediate-level components, where a redundant calibration unit is introduced to calibrate the analog domain calculation results of intermediate-level components. This method adjusts the weight values of the calibration memristor array based on the deviation between actual and target output data, ensuring accurate calibration without altering the existing weight matrix of the memristor array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a calibration unit is introduced to calibrate the analog domain calculation results, then the accuracy of calculation results is improved, but the device complexity increases
Solution Approach 1:
The patent divides the calibration process into two levels: component-level calibration (calibrating individual memristor weights) and intermediate-level calibration (calibrating calculation results at the processing element level). The intermediate-level calibration unit operates at a higher abstraction level, calibrating the output of the memristor array rather than each individual component, thus reducing the complexity multiplier while still improving overall accuracy.
Solution Approach 2:
The patent introduces an intermediary calibration memristor array that works in conjunction with the calculation memristor array. This intermediary structure allows for result calibration without requiring direct modification of the original calculation weights, enabling accurate calibration while maintaining a manageable hardware overhead through a structured intermediary layer.
2Measurement precision
If each bottom-level component is calibrated, then the accuracy is improved, but the additional overhead increases
Solution Approach 1:
The patent segments the calibration task between two levels: fine-grained component calibration of the calibration memristor array and coarse-grained system-level calibration. By performing calibration at the intermediate level (processing element level) rather than exclusively at the bottom level, the patent reduces the total number of calibration operations and hardware resources required while maintaining accuracy.
Solution Approach 2:
Instead of calibrating every single bottom-level memristor component, the patent applies partial calibration at the intermediate level. The calibration memristor array provides sufficient calibration capability without requiring exhaustive component-level calibration, achieving the necessary accuracy with reduced overhead through partial action at a higher level.
Data Source
AI summary
A storage and computation integrated apparatus and a calibration method therefor. The storage and computation integrated apparatus includes a first processing unit, which includes: a first computation memristor array; a first calibration memristor array; and a first processing unit. The calibration method includes: determining, by means of off-chip training, a first computation weight matrix which corresponds to a first computation memristor array, and writing the first computation weight matrix into the first computation memristor array; and on the basis of the first computation memristor array where the first computation weight matrix has been written and the first computation weight matrix, performing on-chip training on a first calibration memristor array, so as to adjust a weight value of the first calibration memristor array.