Memristor Crossbar On-Chip Training via Analog Error Propagation
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Solution Overview
Problem
Conventional neuromorphic computing networks require significant physical space and power, limiting their application in industries such as biomedical, military, and mobile devices due to their large scale and high energy consumption.
Innovation Solution
An analog neuromorphic circuit utilizing resistive memories, comparators, and resistance adjusters that implement parallel processing by adjusting resistance values based on error signals to minimize the difference between output and desired signals, enabling efficient computation with reduced power and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional neuromorphic computing networks are implemented in large scale computer clusters, then computation power is improved, but physical space and power consumption increase significantly
Solution Approach 1:
The patent replaces conventional digital computing mechanisms with analog neuromorphic computing using resistive memories (memristors). The crossbar architecture performs computations through analog voltage signals and resistive elements, substituting traditional digital logic operations with physical analog processes that consume less power. The memristive devices inherently perform multiplication and accumulation operations through their resistance characteristics, eliminating the need for high-power digital processors.
Solution Approach 2:
The patent changes the operating parameters from digital voltage levels to analog voltage signals that continuously vary. The resistive memories operate with analog resistance values that represent weights, and computations are performed using analog voltage divisions and current flows. This parameter change from discrete digital states to continuous analog states enables parallel processing and reduces power consumption while maintaining computation power.
2Power
If conventional neuromorphic computing networks are implemented in large scale computer clusters, then computation power is improved, but physical space occupied increases
Solution Approach 1:
The patent merges multiple functions into the resistive memory crossbar structure. The same physical device performs both storage (resistance values represent weights) and computation (analog voltage signals perform multiplication and accumulation). This merging of storage and processing functions eliminates the need for separate memory and processor units, significantly reducing the physical space required compared to conventional computer clusters.
Solution Approach 2:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking of resistive memory crossbars. Multiple computational layers are stacked vertically, with each layer performing computations in parallel. This dimensional change enables exponential increase in computation power while maintaining a compact footprint, as the system scales in the vertical dimension rather than requiring proportional horizontal expansion.
3Device complexity
If chronological order of operation execution is used in conventional microprocessors, then device complexity is reduced, but productivity decreases
Solution Approach 1:
The patent implements continuous analog processing where voltage signals flow continuously through the resistive memory crossbar, performing computations in parallel without discrete clock cycles. Multiple operations occur simultaneously as analog signals propagate through the network, eliminating the sequential execution bottleneck. The continuous nature of analog voltages allows unlimited parallel operations to occur concurrently, dramatically increasing productivity while maintaining simplicity through the natural physics of voltage division and current flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for significant computational efficiency with minimal power consumption and compact size, enabling applications like image recognition and learning algorithms in previously unsuitable platforms.
Implementation Method 1
A plurality of resistive memories is configured to provide a resistance to the input voltage signal as the input voltage signal propagates through the plurality of resistive memories generating a first output voltage signal
Implementation Method 2
A first comparator is configured to compare the first output voltage signal to a desired output signal and generate the first error signal that is representative of a difference between the first output voltage signal and the desired output signal
Implementation Method 3
A resistance adjuster is configured to adjust a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal
Data Source
AI summary
An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.