Memristor Crossbar Neural Network Accelerator
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Solution Overview
Problem
Implementing artificial neural networks is highly computation-intensive and resource-hungry, making it challenging to optimize them using general processors, and memristor-based crossbar arrays face issues with sneak path currents in larger arrays, affecting accuracy and efficiency in vector-matrix computations.
Innovation Solution
Hardware accelerators utilizing memristor-based crossbar arrays programmed with weight matrices to calculate node values for neural networks, incorporating access transistors or non-linear selectors to minimize sneak path currents, and employing current comparators to generate new node values by comparing output currents with threshold currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memristor-based crossbar arrays are used for vector-matrix computations, then computation speed and efficiency are improved, but sneak path currents increase in larger arrays affecting accuracy
Solution Approach 1:
Access transistors are introduced as intermediary components between the input lines and memristor crossbar arrays. These transistors act as switches that selectively enable or disable current paths, preventing sneak path currents from flowing through unintended memristors while still allowing valid computation currents to pass through the programmed weight matrix paths.
Solution Approach 2:
The memristor crossbar array is divided into smaller computational units or blocks, each with its own set of access transistors. This segmentation isolates sneak path currents to local regions rather than allowing them to propagate across the entire array, thereby maintaining computation accuracy in larger systems while preserving the parallel computation advantages.
2Adaptability or versatility
If general processors are used to implement neural networks, then flexibility and ease of programming are maintained, but resource consumption and computation time increase significantly
Solution Approach 1:
The patent replaces traditional von Neumann architecture processors with a memristor-based hardware accelerator that directly implements neural network computations using electrical current flows through the crossbar array. This substitution eliminates the need for sequential processing, memory access, and complex control logic, dramatically reducing energy consumption while maintaining adaptability through programmable weight matrices.
Solution Approach 2:
The memristor crossbar array is designed as a universal computing platform that can be reconfigured for different neural network architectures and applications by simply programming different weight matrices into the memristors. This multi-functionality allows the same hardware to efficiently execute various neural network models without requiring dedicated hardware for each specific application.
3Power
If larger memristor arrays are used to increase computational capacity, then processing power improves, but sneak path currents become more severe affecting reliability
Solution Approach 1:
Access transistors serve as mediator components that are scaled with the array size. As the crossbar array grows larger to increase processing power, the corresponding increase in access transistors ensures that each additional memristor is properly controlled, preventing sneak path currents from compromising the reliability of the expanded system.
Solution Approach 2:
The patent introduces a control dimension through the access transistor gate terminals, which provides an additional degree of freedom for managing current flow. By controlling the gate voltages of access transistors, the system can selectively activate specific rows or columns in the crossbar array, enabling larger arrays to be used reliably by controlling current paths in a dimension orthogonal to the computational data flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient hardware calculations of node values for neural networks, reducing resource requirements and improving accuracy by leveraging memristor-based crossbar arrays with minimized sneak path currents, facilitating faster and more accurate neural network computations.
Implementation Method 1
an input voltage signal from each row line of the crossbar is weighted by the conductance of the resistive devices in each column line and accumulated as the current output from each column line
Implementation Method 2
Large crossbar arrays of memory devices with memristors can be used in a variety of applications, including memory, programmable logic, signal processing control systems
Implementation Method 3
Memristors are devices that can be programmed to different resistive states by applying a programming energy, such as a voltage
Data Source
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AI summary
Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator to compare an output current from the crossbar array to a threshold current according to an update rule to generate new node values. The crossbar array has a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, where the memory cells are programmed according to a weight matrix. The plurality of row lines are to receive an input vector of node values, and the plurality of column lines are to deliver an output current to be compared with the threshold current.