Memristor Crossbar Circuit for Parallel String Matching
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Solution Overview
Problem
Current memory hardware faces challenges in reducing power consumption and size while maintaining efficiency in applications like neuromorphic computing and cybersecurity, where parallel string matching is required, as conventional CMOS systems are power-intensive and have limitations in density and cooling.
Innovation Solution
The use of memristor crossbar circuits for highly parallel string matching, which utilize memristors with programmable resistance to enable low-power, high-density storage and comparison of input data against multiple target words, eliminating the need for transistors and reducing energy consumption by leveraging self-biasing and non-volatile properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional CMOS systems are used for parallel string matching, then computation capability is achieved, but power consumption is high and device size is large
Solution Approach 1:
The patent replaces conventional CMOS electronic switching systems with a memristor-based crossbar array that uses analog conductance states to perform parallel string matching. The memristor crossbar utilizes voltage division and current measurement to determine matches, eliminating the need for transistor-based logic circuits and significantly reducing power consumption while maintaining parallel processing capability.
Solution Approach 2:
The patent uses multiple copies of the same memristor crossbar circuit to handle different target words simultaneously. Each crossbar column represents a target word, and all columns operate in parallel to compare against the input string, enabling highly parallel string matching without increasing per-unit complexity.
2Quantity of substance
If conventional CMOS systems are used for memory hardware, then storage capability is achieved, but device density is limited and cooling requirements increase
Solution Approach 1:
The patent transitions from planar CMOS transistor arrangements to a three-dimensional memristor crossbar architecture where memory elements are arranged in vertical stacks and multiple layers can be integrated. This dimensional change enables significantly higher device density by utilizing vertical space and reducing the footprint of each memory cell.
3Area of stationary object
If memristor crossbar circuits are used for parallel string matching, then power consumption is reduced and area is reduced, but circuit complexity increases
Solution Approach 1:
The patent designs a universal memristor crossbar circuit that can store multiple target words and perform string matching against any input string of the same length. The same hardware structure handles all matching operations through parallel column operations, eliminating the need for separate circuits for each target word and reducing overall system complexity despite the sophisticated individual cell design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significant power savings, area reduction, and improved energy efficiency, especially at lower frequencies, making it suitable for applications like UAVs and intrusion detection, while maintaining competitive search times and densities compared to CMOS alternatives.
Implementation Method 1
memristors with programmable resistance to enable low-power, high-density storage and comparison
Implementation Method 2
leveraging self-biasing and non-volatile properties
Implementation Method 3
leveraging self-biasing and non-volatile properties
Data Source
AI summary
A crossbar circuit determines a match of N bits of data to at least one of M target words simultaneously. The circuit comprises N inputs (one per data bit) and M outputs (one per target word). For each of the M target words, the circuit comprises N−1 biased bits, where each biased bit includes a first data memristor coupled to a corresponding one of the N inputs; a second data memristor coupled to the corresponding one of the N inputs, where the corresponding one of the N inputs is inverted before reaching the second data memristor; and two biasing memristors. Further, the circuit comprises a general bit comprising a first data memristor coupled to the input that does not correspond to any of the biased bits; and a second data memristor coupled to the input that does not correspond to any of the biased bits and is inverted.