Device and method for hardware-based data encryption with complementary resistance switches
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Solution Overview
Problem
Software-based encryption methods are inefficient and energy-intensive, particularly as data volumes grow, and they have a security vulnerability related to the predictability of memristor-based physical unclonable functions (PUFs) used in hardware-based cryptography.
Innovation Solution
A hardware-based encryption system utilizing a memristor with two reconfigurable barriers and multiple random number generators for encoding and decoding binary data, where the memristor's resistance is adjusted by different voltage pulses to create non-volatile states that can only be decrypted with the identical memristor and random number generators used for encryption, enhancing security by making decryption difficult for attackers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software-based encryption is used, then data can be encrypted and decrypted, but considerable time and computing effort are required along with increased energy consumption
Solution Approach 1:
The patent replaces software-based encryption mechanisms with hardware-based encryption using memristors. The memristor device physically encodes cryptographic keys through its resistance states, eliminating the need for software processing during encryption and decryption operations. This hardware implementation directly addresses the contradiction by providing faster operation with lower energy consumption compared to software-based approaches.
2Productivity
If memristor-based PUFs are used for hardware encryption, then encryption efficiency improves, but security vulnerability arises due to predictability of individual memristor characteristics
Solution Approach 1:
The patent merges multiple individual memristor characteristics into a collective cryptographic key. Instead of relying on a single memristor's unpredictable properties, the system combines the resistance characteristics of multiple memristors to form a composite key that is both efficient for hardware operations and secure against prediction attacks. This merging approach resolves the contradiction by maintaining encryption efficiency while improving security reliability.
Solution Approach 2:
The patent creates a composite cryptographic solution by integrating multiple memristor elements with different resistance characteristics. The composite key derived from multiple memristors provides enhanced security compared to individual memristors, as predicting the collective behavior becomes computationally infeasible even if individual characteristics show some predictability. This composite approach maintains hardware encryption efficiency while addressing security concerns.
3Reliability
If identical memristor and random number generator are required for decryption, then security against unauthorized access improves, but device complexity increases
Solution Approach 1:
The patent implements a replicable memristor array configuration that can be manufactured with identical structural parameters. While the physical memristors are copies of the same design, their individual resistance characteristics remain unique due to manufacturing variations. This copying approach allows the system to maintain security through identical hardware configurations while the inherent physical variations provide the necessary unpredictability for secure decryption.
Solution Approach 2:
The patent utilizes the natural parameter variations in memristor resistance values as the basis for cryptographic security. Instead of trying to control or standardize resistance values, the system embraces the parameter variations that occur during manufacturing. Each memristor's unique resistance profile becomes part of the cryptographic key, allowing identical hardware designs to produce secure, unpredictable decryption capabilities without increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves encryption efficiency, reduces system load, and closes the security gap in memristor-based data transmission by ensuring only the original encryption hardware can decrypt the data, providing robust protection against unauthorized access.
Implementation Method 1
Due to the stochastic behavior of memristors, they are ideal potential candidates for the implementation of encryption hardware. Memristors are novel microelectronic components whose electrical resistance can be specifically adjusted depending on the current flow and then remains non-volatile without the application of external voltage
Implementation Method 2
US 2015/0358151 A1 discloses a complementary resistance switch having two outer terminals between which two piezoelectric or ferroelectric layers with an inner terminal are located
Implementation Method 3
US 2015/0358151 A1 discloses a complementary resistance switch having two outer terminals between which two piezoelectric or ferroelectric layers with an inner terminal are located
Data Source
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AI summary
An encoder (100) for encoding an input binary value of a binary input data sequence by generating an output current signal is provided. The encoder (100) comprises a control module (110) and a switchable resistor element (120). The switchable resistor element (120) is configured to be in either a first state or another second state depending on a first input voltage at a first time and depending on a second input voltage at a later second time. The control module (110) is configured to apply the first input voltage to the switchable resistor element (120) at the first time such that the first input voltage depends on said input binary value.Furthermore, the control module (110) is configured to apply the second input voltage to the switchable resistor element (120) at the second time point, such that the second input voltage depends on a pseudorandom binary value from a plurality of pseudorandom binary values of a first binary pseudorandom data sequence. Furthermore, the control module (110) is configured to apply a third input voltage to the switchable resistor element (120) at a third time point after the second time point, such that the third input voltage depends on said pseudorandom binary value from the plurality of pseudorandom binary values of the first binary pseudorandom data sequence or on a pseudorandom binary value from a plurality of pseudorandom binary values of a second binary pseudorandom data sequence.The switchable resistor element (120) is configured to output the said output current upon application of the third input voltage at the third time, such that the said output current depends on the third input voltage and on whether the switchable resistor element (120) is in the first state or in the second state.