Memristor In-Memory Computing With Hybrid Dispatch for DNN Flexibility
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Solution Overview
Problem
The existing memristor-based in-memory computing architecture lacks flexibility, efficiency, and versatility, as it is primarily designed for specific applications and lacks a general-purpose architecture capable of deploying various deep neural network architectures across different tasks and scenarios.
Innovation Solution
An in-memory computing processor with a hybrid dispatch architecture that integrates a master control unit and memristor processing modules, allowing for both direct communication and control, supporting fine-grained operator-level and coarse-grained algorithm-level acceleration, and enabling flexible deployment of neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a simple macro-array chip structure is used, then manufacturing complexity is reduced, but flexibility and versatility for different neural network architectures are insufficient
Solution Approach 1:
The chip is divided into multiple processing modules, each capable of independent operation. This segmentation allows the system to handle different neural network architectures by activating specific modules while maintaining a relatively simple overall structure that is easier to manufacture.
Solution Approach 2:
Each processing module is designed with universal functionality to support multiple neural network operations. The modules can be configured to handle different computational tasks through programmable control, providing versatility without requiring complex custom hardware for each application.
2Productivity
If a highly customized dedicated chip is used, then efficiency for specific applications is improved, but flexibility for different tasks and scenarios is reduced
Solution Approach 1:
The chip employs dynamic reconfiguration capabilities where processing modules can be programmatically assigned to different computational tasks. This dynamic adaptability allows the system to optimize efficiency for specific applications while maintaining flexibility to switch between different neural network architectures and computational patterns.
Solution Approach 2:
The system changes operational parameters through software control rather than hardware reconfiguration. By adjusting control signals and operational modes, the chip can optimize performance for different neural network types without physical modifications, balancing efficiency and flexibility.
3Stability of the object's composition
If data migration between storage and computation is required, then traditional computing architecture is maintained, but access latency and energy consumption increase
Solution Approach 1:
The patent merges storage and computation functions within the same processing modules. Memristor arrays are directly integrated with processing units, allowing data to remain in place during computation and eliminating the need for repeated data migration between separate storage and computing components.
Solution Approach 2:
The system introduces intermediate buffer structures and direct memory access pathways that reduce the latency of data access. These intermediary components facilitate efficient data transfer within the processor without requiring full data migration to external storage, reducing both time loss and energy consumption.
4Measurement precision
If fine-grained operator-level control is implemented, then computational precision is improved, but system complexity increases
Solution Approach 1:
The control system is segmented into hierarchical levels, with each processing module having its own control unit that manages fine-grained operations independently. This segmentation allows precise control of individual operators while distributing complexity across multiple manageable units rather than requiring a single complex control system.
Solution Approach 2:
Each processing module is equipped with self-control capabilities that allow it to manage its own operations autonomously. This self-service approach enables fine-grained computational precision at the module level without requiring complex external control, as each unit independently manages its own precision-critical operations.
Data Source
AI summary
An in-memory computing processor, an in-memory computing processing system, an in-memory computing processing apparatus, and a deployment method of an algorithm model based on the in-memory computing processor are disclosed. The in-memory computing processor includes a first master control unit and a plurality of memristor processing modules, and the first master control unit is configured to be capable of dispatching and controlling the plurality of memristor processing modules, the plurality of memristor processing modules are configured to be capable of calculating under the dispatch and control of the first master control unit, and the plurality of memristor processing modules are further configured to be capable of communicating independently of the first master control unit to calculate.