Memristor Crossbar MAC Circuits Without Row Sample-and-Hold
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing artificial neural networks require sample-and-hold circuits for each row line to synchronize currents flowing through memristor-based analog multiplier-accumulators, increasing chip space and cost due to the need for simultaneous voltage application across row lines.
Innovation Solution
A distributed digital-to-analog conversion architecture with column output circuits that include integration capacitors and current mirroring circuitry, allowing currents to flow at different timings and eliminating the need for per-row sample-and-hold circuits by using an integration control signal to mirror currents onto capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sample-and-hold circuits are added to each row line to synchronize currents, then current synchronization is improved, but chip space and cost increase
Solution Approach 1:
The patent removes the sample-and-hold circuits from each row line, extracting the problematic component that caused chip space increase. Instead of having distributed sample-and-hold circuits throughout the array, the design eliminates them entirely and uses a different approach to achieve the necessary current control and synchronization functionality.
Solution Approach 2:
The patent implements periodic switching of row lines in time-multiplexed fashion, where voltages are applied to row lines sequentially rather than simultaneously. This periodic action allows currents to flow at different timings without requiring sample-and-hold circuits, as each row is activated in turn during specific time periods.
2Reliability
If simultaneous voltage application across row lines is implemented, then current synchronization is improved, but device complexity increases
Solution Approach 1:
The patent replaces simultaneous voltage application with periodic voltage application to row lines. By switching row lines on and off in a time-multiplexed sequence controlled by clock signals, the system achieves proper current timing without the complexity of simultaneous control mechanisms. The column output circuits process currents from different time periods through integration capacitors, maintaining operational accuracy.
Solution Approach 2:
The patent introduces integration capacitors at column output circuits as intermediary elements. These capacitors accumulate and integrate currents from different time periods, acting as mediators that combine the time-multiplexed currents into a unified output signal. This intermediary approach simplifies the overall system by removing the need for complex simultaneous voltage application control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces chip space and cost by enabling efficient generation of output signals without the need for sample-and-hold circuits, while maintaining accurate multiply-accumulate operations across memristor-based analog multiplier-accumulators.
Implementation Method 1
a first electrode of the integration capacitor Cint may be connected to the switch S1 and a second electrode of the integration capacitor may be connected to a high voltage Vdd... the magnitude mirrors a current flowing on the column line
Data Source
AI summary
An example electronic device includes a crossbar array, row driver circuitry, and column output circuits for each of the column lines of the crossbar array. The crossbar array may include row lines, column lines, and memristors that each are connected between one of the row lines and one of the column lines. The row driver circuitry may be to apply a plurality of analog voltages to a first node during a plurality of time periods, respectively, and, for each of the row lines, selectively connect the row line to the first node during one of the plurality of time periods based on a digital input vector. The column output circuits may each include: an integration capacitor, a switch that is controlled by an integration control signal, and current mirroring circuitry. The current mirroring circuitry may be to, when the switch is closed, flow an integration current to or from an electrode of the integration capacitor whose magnitude mirrors a current flowing on the corresponding column line. The integration control signal may be to close the switch for a specified amount of time during each of the plurality of time periods.