Memristor Neural Network Circuit Error Detection
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Solution Overview
Problem
In neural network circuits using memristors, it is challenging to detect and correct data errors due to the integration of memory cells and computing circuits, making it difficult to determine defects in memristors arranged in a matrix without significant time consumption or requiring spare elements for replacement.
Innovation Solution
A neural network circuit design that includes memristors connected in a matrix, with a voltage application device, a controller for data management, and current-to-voltage conversion amplifier circuits, allowing for error detection and correction by adjusting current values to zero, thereby identifying and correcting abnormal resistance values in memristors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memristors are arranged in a matrix for neural network computation, then computing efficiency is improved, but error detection capability deteriorates
Solution Approach 1:
The patent divides the memory device into multiple banks, with each bank containing a subset of the memristor matrix. This segmentation allows independent error detection and correction for each bank, enabling the system to maintain high computing efficiency while improving reliability through localized error handling without requiring system-wide spare elements.
Solution Approach 2:
The patent introduces sense amplifiers as intermediary components between the memristor matrix and the readout circuitry. These sense amplifiers not only perform the necessary signal amplification but also enable error detection by comparing complementary bit lines, thus maintaining computing efficiency while adding error detection capability through the intermediary function.
2Reliability
If spare elements are used for replacement, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service error correction by utilizing the existing memristor cells and sense amplifiers to detect and correct errors within the same array. The differential read operation allows the system to self-diagnose errors by comparing complementary bit lines, eliminating the need for external spare elements or complex replacement circuits.
Solution Approach 2:
The patent makes the sense amplifiers multi-functional by having them perform both the necessary signal amplification for normal operation and error detection through differential comparison. This universality allows the same components to serve dual purposes, improving reliability without adding dedicated error correction hardware that would increase device complexity.
3Reliability
If error detection is implemented, then reliability is improved, but time consumption increases
Solution Approach 1:
The patent performs error detection during the normal read operation itself by using differential comparison of complementary bit lines. The error detection is built into the read process, so no additional time-consuming error checking step is required. The system preliminarily prepares the complementary bit lines during the read operation, enabling simultaneous data retrieval and error detection.
4Productivity
If memory cells and computing circuits are integrated, then productivity is improved, but difficulty of detecting and measuring errors increases
Solution Approach 1:
The patent uses asymmetric bit line pairing where each memristor cell is connected to complementary bit lines (BL0 and BL1) that are read differentially. This asymmetric connection scheme creates a natural error detection mechanism where errors in one bit line can be detected by comparing with its complement, making error detection straightforward despite the integrated memory-computing architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient detection and correction of memory element defects within the neural network circuit, ensuring data reliability without the need for extensive time or spare elements, by utilizing current adjusters to set and reset resistance values based on writing states.
Implementation Method 1
memristors being variable resistance elements connected in a matrix, wherein the memristors act as memory elements and resistance values of the memristors provide data of the memory device
Implementation Method 2
each current adjuster being arranged to adjust a total current value input to a corresponding I-/V conversion amplification circuit to zero
Data Source
AI summary
A neural network circuit is provided. The neural network circuit includes a memory device including memristors connected in a matrix, a controller arranged to control a voltage application device to perform writing, deleting and reading data in the memory device, multiple current-to-voltage (I-V) conversion amplifier circuits arranged to convert currents flowing through the memory elements into voltages and outputting the voltages, and multiple current adjusters respectively corresponding to the I-V conversion amplification circuits, each current adjuster being arranged to adjust a total current value input to a corresponding I-/V conversion amplification circuit to zero.