Memristor Non-Volatile Memory Cell With Transistor Access Circuit
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Solution Overview
Problem
Current memory architectures face challenges in achieving high data stability, low power consumption, simple structure, and fast reading/writing speeds, particularly in mobile devices where space and power efficiency are critical.
Innovation Solution
A memristor-based non-volatile memory device is developed, utilizing a configuration of three transistor switches and two memristors to achieve fast reading and writing speeds similar to SRAM, with the ability to store data persistently even after power is cut off, by employing memristors with different impedance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If ROM or flash memory is used for non-volatile storage, then data stability is improved, but writing and reading speeds deteriorate
Solution Approach 1:
The patent merges the advantages of SRAM (fast reading/writing) and non-volatile memory (data stability) by integrating memristors with a transistor-based access circuit. The memory cell combines volatile and non-volatile elements to achieve both fast access speeds and persistent data storage, resolving the contradiction between speed and stability.
Solution Approach 2:
The patent utilizes the variable resistance property of memristors, changing their resistance state between high and low impedance levels to represent binary data. This parameter change enables fast writing speeds comparable to SRAM while maintaining non-volatile data stability, as the resistance state persists without power.
2Device complexity
If DRAM is used for volatile memory, then structure simplicity and storage density are improved, but power consumption increases due to periodic capacitor charging
Solution Approach 1:
The memristor-based memory cell automatically maintains its data state without requiring periodic refresh operations. The resistive state of the memristor persists naturally without external intervention, eliminating the need for capacitor charging circuits and associated power consumption while maintaining structural simplicity.
3Speed
If SRAM is used for volatile memory, then reading and writing speeds are improved, but manufacturing cost and circuit space increase due to requiring six or more transistors per byte
Solution Approach 1:
The patent extracts the memory storage function from the transistor network and assigns it to the memristor element. This reduces the transistor count from six or more (in conventional SRAM) to a minimal access circuit, significantly reducing circuit space while preserving fast reading and writing speeds through the memristor's inherent resistive switching capability.
4Speed
If conventional SRAM is used, then reading and writing speeds are improved, but data stability deteriorates when power supply is cut off
Solution Approach 1:
The patent creates a composite memory cell structure combining volatile (transistor) and non-volatile (memristor) elements. The transistor provides fast switching and access control, while the memristor provides persistent data storage. This composite structure achieves both fast reading/writing speeds and data stability after power loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a compact, energy-efficient non-volatile memory with SRAM-like performance, suitable for various integrated circuits, including programmable circuits and content addressable memory, improving data stability and reducing power consumption.
Implementation Method 1
Each non-volatile memory cell includes a first switch, a first memristor, a second switch, a second memristor and a third switch. The control terminal of the first switch is coupled to the word line. The first memristor is configured as having a first impedance. The control terminal of the second switch is coupled to the word line. The second memristor is configured as having a second impedance.
Data Source
AI summary
A non-volatile memory device includes plural non-memory cells. Each non-volatile memory cell includes a first switch, a first memristor, a second switch, a second memristor and a third switch. The control terminal of the first switch is coupled to a word line. The first memristor is provided with a first impedance. The control terminal of the second switch is coupled to the word line. The second memristor is provided with a second impedance. The first switch, the first memristor, the second switch and the second memristor are serially connected between a bit line and an inverted bit line in an alternate manner. The third switch is used for configuring the first impedance and the second impedance. The non-volatile memory device provided by the disclosure has a characteristic of quick access and the data stored therein does not require a dynamic update.