Memristor Spiking Architecture for Neural Network Compute
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Solution Overview
Problem
Existing neural network architectures, particularly spiking neural networks, face challenges in accurately processing inputs without disturbing the storage properties of memristor components due to improper voltage application, leading to errors and noise in multiply accumulate functions.
Innovation Solution
The implementation of a memristor spiking architecture that isolates memristor components from voltage disturbances, using a memristor-based circuitry to perform accurate spiking operations without affecting stored values, enabling efficient processing in asynchronous neural networks and multi-stage compute processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If voltage is applied to memristor components for spiking operations, then spiking capability is enabled, but storage properties are disturbed leading to errors and noise
Solution Approach 1:
The patent divides the memristor system into separate functional components: storage memristors that maintain weight values and compute memristors that perform spiking operations. This segmentation allows voltage to be applied to compute memristors without disturbing the storage memristors, resolving the contradiction between enabling spiking capability and maintaining storage integrity.
Solution Approach 2:
The patent introduces crossbar array architecture as an intermediary structure where storage and computation occur in separate spatial domains. The crossbar array enables multiply-accumulate operations through analog voltage distribution without directly applying disruptive voltages to the stored weight values, thus protecting storage properties while enabling spiking operations.
2Device complexity
If memristor components are used for both storage and computation, then device complexity is reduced, but processing accuracy deteriorates due to noise and interference
Solution Approach 1:
The patent segments the memristor crossbar array into distinct storage regions and computation regions. Weight values are stored in specific memristors while separate memristors perform compute operations. This spatial segmentation maintains low device complexity by using uniform memristor technology throughout while improving processing accuracy by isolating computation-induced noise from stored values.
3Productivity
If voltage is applied to perform multiply accumulate functions, then computation is enabled, but noise and errors are introduced in the process
Solution Approach 1:
The patent uses the crossbar array architecture as an intermediary computation platform where analog voltages represent data and weights. The physical layout and circuit design of the crossbar array enable multiply-accumulate operations through controlled voltage distribution, allowing computation to proceed while the architecture itself filters and manages noise through its inherent analog computing properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for accurate spiking capabilities in neural networks and image processing applications, reducing noise and interference while maintaining the integrity of memristor storage properties, thereby enhancing the efficiency and accuracy of multi-stage compute processes.
Implementation Method 1
a memristor component to store a weight value
Implementation Method 2
applying an input voltage across a memristor component to obtain a current output
Implementation Method 3
isolates memristor components from voltage disturbances, using a memristor-based circuitry to perform accurate spiking operations without affecting stored values
Data Source
AI summary
A circuit for a neuron of a multi-stage compute process is disclosed. The circuit comprises a weighted charge packet (WCP) generator. The circuit may also include a voltage divider controlled by a programmable resistance component (e.g., a memristor). The WCP generator may also include a current mirror controlled via the voltage divider and arrival of an input spike signal to the neuron. WCPs may be created to represent the multiply function of a multiply accumulate processor. The WCPs may be supplied to a capacitor to accumulate and represent the accumulate function. The value of the WCP may be controlled by the length of the spike in signal times the current supplied through the current mirror. Spikes may be asynchronous. Memristive components may be electrically isolated from input spike signals so their programmed conductance is not affected. Positive and negative spikes and WCPs for accumulation may be supported.