Memristor Synapse Array for Dynamic CNN Attention Computing
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Solution Overview
Problem
Existing computing technologies face inefficiencies in performing dynamic convolution neural network computations, particularly in terms of energy consumption and storage capacity, especially when handling complex tasks like image classification.
Innovation Solution
A neuromorphic computing device utilizing memristor elements for synapse arrays, which generates input and gate voltages to perform dynamic convolution computations, incorporating synapse elements with drain, gate, and source terminals to facilitate efficient kernel and attention weight computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional semiconductor devices are used for neural network computations, then the device structure is well-established and easy to manufacture, but energy consumption is high and storage capacity is limited
Solution Approach 1:
The patent replaces traditional semiconductor devices with memristor elements that utilize electrical characteristics and state changes to perform computations. The memristor's ability to maintain state through electrical characteristics enables in-memory computing, substituting the von Neumann architecture with a system where storage and computation occur in the same physical location, thereby reducing energy consumption while maintaining manufacturability through electrical signal control
Solution Approach 2:
The memristor element serves multiple functions simultaneously: it acts as both a storage device (maintaining state) and a computing device (performing computations through state changes). This multi-functionality eliminates the need for separate memory and processing units, reducing overall system energy consumption while the electrical control mechanism ensures ease of integration and manufacture
2Speed
If existing computing technologies are used for dynamic convolution neural networks, then the system is simple to implement, but data access speed is slow and storage capacity is limited
Solution Approach 1:
The patent introduces a three-terminal memristor structure (drain, gate, source) that adds a dimensional aspect to the traditional two-terminal device. This additional terminal enables independent control of channel current through gate voltage while maintaining state through drain-source voltage, creating a new dimension of control that simultaneously improves data access speed and manages system complexity through modular architecture
Solution Approach 2:
The computing system is segmented into multiple synapse elements arranged in arrays, with each element handling specific computations. This segmentation allows parallel processing of neural network operations, improving overall data access speed while each individual memristor element remains relatively simple in structure, balancing speed improvement with manageable complexity
3Quantity of substance
If memristor elements are used for synapse arrays, then storage capacity and data access speed are improved, but the device structure becomes more complex
Solution Approach 1:
The patent applies local quality by assigning specific functions to specific terminals of the memristor element: the drain terminal handles state maintenance through voltage application, the gate terminal controls channel current for computation, and the source terminal provides the reference potential. This localized functional assignment increases storage capacity through precise state control while keeping each terminal's structure relatively simple and well-defined
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves faster data access speeds and higher storage capacity by dynamically adjusting attention weights, enhancing the efficiency and performance of convolution neural network operations.
Implementation Method 1
The synapse element is a memristor element including a drain terminal to which one of the plurality of input voltages is applied, a gate terminal to which one of the plurality of gate voltages is applied
Data Source
AI summary
Disclosed is a neuromorphic computing device, which includes an input voltage generator that generates a plurality of input voltages based on input data, a gate voltage generator that generates a plurality of gate voltages based on the input data, and a convolution computing device including a synapse array circuit to which the plurality of input voltages and the plurality of gate voltages are applied, and the synapse array circuit includes a plurality of synapse elements, and the synapse element is a memristor element including a drain terminal to which one of the plurality of input voltages is applied and a gate terminal to which one of the plurality of gate voltages is applied.