MEMS Actuator Layer Topography for Uniform Lithography
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Solution Overview
Problem
Existing methods for reducing MEMS device size often increase die size or complicate processing by focusing on standoff height or distance, leading to non-uniform photoresist thickness and lithography variations.
Innovation Solution
A method involving fusion bonding a handle wafer to a device wafer, depositing a hardmask and dielectric layers, forming vias with conductive fill, and using a eutectic bond layer to etch MEMS patterns, while employing nonconductive standoffs for manufacturability and reducing standoff height without increasing die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If standoff height is increased to maintain photoresist thickness uniformity, then lithography precision is improved, but die size increases
Solution Approach 1:
The patent introduces a vertical dimension solution by creating a recessed area in the MEMS device surface, allowing the photoresist to be deposited at a reduced height while maintaining sufficient thickness for patterning. This dimensional change enables smaller die size without compromising lithography precision.
Solution Approach 2:
The patent applies local quality by creating a specific recessed geometry only where needed for photoresist deposition, while the rest of the MEMS device maintains its original structure. This localized modification optimizes photoresist thickness uniformity without unnecessarily increasing overall die size.
2Area of stationary object
If standoff height is reduced to decrease die size, then area is reduced, but photoresist thickness uniformity deteriorates
Solution Approach 1:
By utilizing the vertical recessed dimension, the patent enables photoresist to be deposited with controlled thickness even when overall standoff height is reduced. The recessed geometry provides a localized volume that accommodates the photoresist layer, maintaining manufacturing precision while reducing die size.
3Manufacturing precision
If distance between standoffs is increased to improve photoresist deposition, then manufacturing precision is improved, but die size increases
Solution Approach 1:
The patent shifts the solution from horizontal spacing (distance between standoffs) to vertical geometry (recessed depth and shape). This allows adequate photoresist deposition quality to be achieved through the recessed volume rather than increased horizontal separation, thereby reducing die size while maintaining manufacturing precision.
4Manufacturing precision
If complex processing steps are added to maintain manufacturability while reducing size, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the photoresist deposition process into two distinct stages: initial deposition in the recessed area, followed by planarization. This segmentation allows each step to be optimized independently, maintaining manufacturing precision without requiring overly complex integrated processing.
Solution Approach 2:
The recessed geometry is created in advance before photoresist deposition, preparing the structure in advance to receive the photoresist layer. This preliminary action simplifies the subsequent deposition process by providing a pre-configured volume that naturally accommodates the photoresist, reducing the need for complex real-time processing adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains manufacturability and reduces die size by controlling photoresist thickness and lithography variations, improving MEMS device fabrication efficiency.
Implementation Method 1
A eutectic bond layer is formed over the conductive material
Implementation Method 2
fusion bonding a handle wafer to a first side of a device wafer
Data Source
AI summary
A method including fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a hardmask on a second side of the device wafer, wherein the second side is planar. An etch stop layer is deposited over the hardmask and an exposed portion of the second side of the device wafer. A dielectric layer is formed over the etch stop layer. A via is formed within the dielectric layer. The via is filled with conductive material. A eutectic bond layer is formed over the conductive material. Portions of the dielectric layer uncovered by the eutectic bond layer is etched to expose the etch stop layer. The exposed portions of the etch stop layer is etched. A micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.