MEMS-ASIC Integrated Package with Microcavity Bonding Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated package solutions for AlN MEMS elements, such as wafer scale vacuum packages and Post-CMOS monolithic integration, face challenges including increased costs and material waste due to mismatched IC and MEMS chip areas, and the flip chip technology cannot form a closed cavity structure, which affects the thermal stability of CMOS circuits and the performance of AlN MEMS elements.
Innovation Solution
An integrated package method and structure that involves forming a closed cavity structure by applying a lithographic process to deposit a re-layout layer, spin-coating an organic compound layer to form a microcavity array, aligning and bonding an electrode connection pad layer, thinning and polishing the silicon substrate, and manufacturing a metal connection member to electrically connect the MEMS element to the ASIC wafer, using materials like benzocyclobutene for bonding and aluminum or copper alloys for connection pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer scale vacuum package technology with TSV is used, then electrical connection between MEMS and ASIC is achieved, but the package structure becomes complicated and IC design is greatly influenced
Solution Approach 1:
The patent divides the package structure into separate functional layers: MEMS element layer, bonding layer with microcavity array, ASIC wafer layer, and connection layer. This segmentation allows each layer to be optimized independently while maintaining electrical connection through the structured bonding interface, reducing overall package complexity compared to monolithic TSV structures.
Solution Approach 2:
The bonding layer with microcavity array serves as an intermediary between the MEMS element and ASIC wafer. This intermediate structure enables electrical connection while providing mechanical support and thermal management, simplifying the overall package design by decoupling the electrical connection function from the structural support function.
2Ease of manufacture
If Post-CMOS monolithic integration is used, then manufacturing process requirements are reduced, but CMOS circuits are greatly affected during high-temperature processing
Solution Approach 1:
The patent performs preliminary actions by completing the MEMS element fabrication and ASIC wafer preparation separately before final integration. The MEMS element is fully formed with its closed cavity structure before bonding to the ASIC wafer, allowing independent optimization of each component without mutual interference during high-temperature processing.
Solution Approach 2:
The manufacturing process is segmented into independent stages: MEMS element fabrication, ASIC wafer preparation, and final bonding integration. This segmentation allows CMOS circuits to be fabricated and tested before MEMS integration, avoiding high-temperature processing effects on sensitive CMOS structures while maintaining ease of manufacture through standardized interfaces.
3Ease of manufacture
If flip chip technology is used, then bonding process is simplified, but closed cavity structure cannot be formed affecting thermal stability
Solution Approach 1:
The bonding layer is designed with local quality variations: regions with microcavities for thermal management and electrical connection, and solid regions for mechanical support. This local differentiation allows the formation of closed cavity structures around MEMS elements while maintaining simplified bonding processes through standardized bonding layer fabrication.
Solution Approach 2:
The patent transitions from traditional planar flip chip bonding to a three-dimensional structure by forming microcavities within the bonding layer. This dimensional change enables closed cavity formation that provides thermal stability and mechanical support while maintaining the simplicity of layer-by-layer fabrication processes.
4Loss of substance
If ASIC area is reduced to match MEMS chip size, then material waste and costs are reduced, but IC scale down speed is slower than MEMS scale down speed
Solution Approach 1:
The bonding layer with microcavity array serves multiple functions: electrical connection, mechanical support, thermal management, and alignment reference. This multi-functionality allows the bonding layer to accommodate area mismatches between MEMS and ASIC while maintaining integration efficiency, eliminating the need for exact size matching and reducing material waste.
Solution Approach 2:
The patent changes the bonding interface from a point-contact flip chip model to a distributed microcavity array model. This parameter change allows flexible area matching between MEMS and ASIC components, enabling efficient use of materials and reducing waste while maintaining high integration productivity through standardized bonding processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a compact, defect-free MEMS element with improved thermal stability and reduced material waste, enabling efficient electrical connection and forming a vacuum closed cavity structure, thus addressing the limitations of existing technologies and enhancing the integration process.
Implementation Method 1
spin-coating an organic compound layer on the re-layout layer to form a bonding layer
Implementation Method 2
applying a lithographic process on an ASIC wafer to deposit and form a re-layout layer
Implementation Method 3
manufacturing a metal connection member on the connection portion and the bonding layer so as to allow the electrode connection pad layer to be electrically connected to the electrical contact area
Data Source
AI summary
An integrated package method for MEMS element and ASIC chip includes forming a re-layout layer on a front surface of an ASIC wafer; coating an organic compound layer on the re-layout layer and applying a lithography process to the organic compound layer to from a microcavity array; aligning and bonding an electrode connection pad layer on a front surface of an MEMS element with the microcavity array to form a closed cavity structure; thinning and exposing a silicon substrate on a back surface of the MEMS element to a desired thickness; applying the lithographic process on the MEMS element to expose the electrode connection pad layer and an electrical contact area of the re-layout layer; and manufacturing a metal connection member connected to the electrode connection pad layer and the electrical contact area. An integrated package structure for MEMS element and ASIC chip is also provided.