MEMS-ASIC Wafer Stacking Without Through Vias for Thin CSP Packaging
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Solution Overview
Problem
Existing methods for manufacturing MEMS devices with integrated ASICs face challenges in achieving reduced dimensions and integrating all system parts in a single Chip Scale Package (CSP) device, while avoiding the use of expensive through vias.
Innovation Solution
A manufacturing process using three wafers - a MEMS wafer, an ASIC wafer, and a carrier wafer - to create a stacked arrangement with reduced thickness, eliminating the carrier wafer and forming a cap with the ASIC wafer, allowing for a single chip integration without through vias, and utilizing common manufacturing steps to achieve low costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through vias are used to stack MEMS die on ASIC die, then electrical connection between layers is achieved, but manufacturing cost increases and integration in single CSP package is not possible
Solution Approach 1:
The patent introduces an organic substrate as an intermediary carrier that enables wafer-level bonding and electrical connection between MEMS and ASIC dice without requiring through vias. The organic substrate serves as a temporary support structure during manufacturing that facilitates low-cost interconnection while allowing final integration in a single CSP package.
Solution Approach 2:
The patent performs wafer-level bonding and electrical connection operations before dicing the individual dice. By establishing interconnections at the wafer level on the organic substrate, the manufacturing process avoids the need for expensive post-dicing through via formation and enables batch processing, significantly reducing manufacturing costs.
2Reliability
If traditional stacking with separate cap and ASIC die is used, then functional requirements are met, but device area and thickness increase
Solution Approach 1:
The patent merges the cap and ASIC die into a single integrated structure by bonding them at wafer level on the organic substrate before dicing. This consolidation eliminates the need for separate packaging of individual components and reduces the overall device thickness while maintaining all functional requirements through direct wafer-level integration.
Solution Approach 2:
The patent transitions from three-dimensional stacked packaging with large footprint to a planar wafer-level integration approach. By performing bonding and interconnection operations in the wafer plane before final stacking, the process achieves compact thickness while maintaining functional performance through optimized dimensional arrangement.
3Ease of manufacture
If carrier wafer is retained in final structure, then manufacturing simplicity is maintained, but final device thickness increases
Solution Approach 1:
The patent extracts and removes the carrier wafer from the final device structure after it has served its purpose during manufacturing and bonding operations. The carrier wafer is used temporarily to facilitate wafer-level processing and bonding, then completely removed to achieve the target thin-profile device thickness while maintaining manufacturing simplicity.
Solution Approach 2:
The carrier wafer is discarded after completing its manufacturing function. The process recovers the bonded MEMS and ASIC dice from the carrier wafer through selective release mechanisms, allowing the carrier to be discarded while preserving the valuable integrated device structure with reduced thickness.
Data Source
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AI summary
Device formed by a first die (210) and a second die (221). The first die is of semiconductor and integrates electronic components (202). The second die has a main surface (210A), forms patterned structures (230) and is bonded to the first die. Internal electrical coupling structures (242) electrically couple the main surface (210A) of the first die (210) to the second die (221). External connection regions (241) extend on the main surface of the first die (210). A package (246) embeds the first die (210), the second die (221) and the internal electrical coupling structures (242) and partially surrounds the external connection regions (241), the external connection regions partially protruding from the package. The second die (221) has through recesses (207, 208) accommodating external connection regions