MEMS Chip Buffer Area Layout for Parasitic Capacitance Isolation

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Solution Overview

Problem

Existing MEMS chips face issues with parasitic capacitance and poor product quality due to potential differences between active and inactive areas, which are exacerbated by foreign matter bridging these areas, leading to leakage.

Innovation Solution

A MEMS chip design featuring insulation loops and a buffer area between the active and inactive areas, made of materials like silicon nitride or silicon oxynitride, with a buffer area of the same material as the active area, connected to both loops, ensuring electrical conduction and enhancing structural durability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If an insulation loop is added to eliminate parasitic capacitance, then sensitivity is improved, but the risk of leakage increases when foreign matter bridges the active and inactive areas

Engineering Contradiction:

ImprovesensitivityVSAvoidleakage risk

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent divides the insulation structure into multiple segments: a first insulation loop, a second insulation loop, and buffer areas between them. This segmentation allows the structure to maintain electrical isolation functionality while creating multiple barriers that foreign matter must cross, thereby reducing leakage risk without compromising sensitivity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces buffer areas as intermediary regions between the active area and the second insulation loop, and between the two insulation loops. These buffer areas serve as intermediate barriers that prevent direct bridging by foreign matter, thus reducing leakage risk while maintaining the parasitic capacitance elimination function.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the width of the insulation loop is increased to prevent foreign matter bridging, then leakage risk is reduced, but the parasitic capacitance elimination effectiveness decreases

Engineering Contradiction:

Improveleakage preventionVSAvoidparasitic capacitance elimination

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

Instead of increasing the width of a single insulation loop, the patent segments the isolation function into multiple narrower loops with buffer areas between them. This maintains the effectiveness of parasitic capacitance elimination by keeping individual loop widths appropriate while achieving better foreign matter prevention through multiple barriers.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimension solution (width of one loop) to a multi-dimensional solution by arranging multiple loops in concentric or nested configurations with buffer areas. This spatial arrangement provides enhanced protection against foreign matter bridging without requiring excessive width in any single loop.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Device complexity

If a single insulation loop is used to separate active and inactive areas, then device complexity is reduced, but the ability to prevent foreign matter bridging is insufficient

Engineering Contradiction:

Improveinsulation structureVSAvoidforeign matter prevention

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent employs multiple insulation loops segmented into a first and second loop with buffer areas between them. This segmented approach enhances foreign matter prevention capability while maintaining relatively simple device complexity, as each loop and buffer area can be integrated into the existing MEMS fabrication process.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively eliminates parasitic capacitance and improves durability by preventing foreign matter from bridging the active and inactive areas, resulting in stable and reliable MEMS performance.

Implementation Method 1

reduce parasitic capacitance in a low-vibration area around the diaphragm

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Implementation Method 2

The inactive area and the back electrode are in electrical conduction with each other

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 3

the back electrode and the induction membrane are located over the back cavity and constitute a capacitor structure

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12515941B2MEMS chip with a buffer area and electric device with the MEMS chip

Publication Date: 2026.01.06 WEIFANG GOERTEK MICROELECTRONICS CO LTD

AI summary

Disclosed are a MEMS chip and an electronic device. The chip can include a substrate having a back cavity, as well as a back electrode and an induction membrane both disposed on the substrate, wherein the back electrode and the induction membrane are located on the back cavity and constitute a capacitor structure, the induction membrane comprises an active area opposite to the back cavity, an inactive area disposed outside the active area, and an isolation area located between the active area and the inactive area, and the isolation area comprises two insulation loops connected to the active area and the inactive area respectively, and a buffer area connected between the two insulation loops, both of the insulation loops being disposed around the active area.