MEMS Device Cap Fabrication via Peripheral TSVs
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Solution Overview
Problem
The existing methods for fabricating monolithic chips with MEMS and CMOS dies require high precision and can cause mechanical stress due to the need for staggering or removing portions of the MEMS die to expose bonding pads, and wire bonding introduces additional stress through resonance frequency.
Innovation Solution
The method involves forming CMOS dice with TSVs on their periphery, stacking them with MEMS dice, and using eutectic bonding to create a monolithic die where TSVs are exposed to facilitate electrical connections without staggering or removing parts of the MEMS die, eliminating the need for wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the CMOS die and MEMS die are staggered to expose the bonding pad on the CMOS die, then the bonding pad can be exposed for electrical connection, but the alignment precision requirement increases and manufacturing complexity increases
Solution Approach 1:
The patent moves the electrical connection interface from the top surface (2D plane) to the side surface (3D dimension) of the MEMS die. By forming conductive vias through the MEMS die thickness and exposing bonding pads on the lateral surface, the electrical connection is achieved in a different spatial dimension, eliminating the need for staggered alignment between CMOS and MEMS dies.
Solution Approach 2:
The conductive vias and side surface bonding pads are formed on the MEMS die before stacking with the CMOS die. This preliminary preparation of electrical connection structures allows subsequent simple planar alignment without requiring complex staggered positioning, reducing manufacturing precision requirements.
2Manufacturing precision
If a portion of the MEMS die is removed to expose the bonding pad on the CMOS die, then the bonding pad can be exposed for electrical connection, but mechanical stress is applied to the monolithic die
Solution Approach 1:
Instead of removing material from the top surface to expose bonding pads, the patent forms conductive pathways through the MEMS die thickness and exposes bonding pads on the lateral surface. This dimensional change allows electrical connection without material removal, eliminating mechanical stress on the monolithic die structure.
3Ease of operation
If wire bonding is used to connect the CMOS die to external components, then electrical connection can be established, but additional stress is introduced through ultrasound resonance
Solution Approach 1:
The patent replaces the mechanical wire bonding process (which uses ultrasound vibration) with a direct bonded connection structure. Conductive vias are formed through the MEMS die and bonded pads are exposed on the side surface, enabling direct electrical connection to external components without ultrasound-induced mechanical stress.
4Device complexity
If the CMOS die is stacked directly on the MEMS die without staggering, then alignment is simplified, but the bonding pad on the CMOS die cannot be exposed
Solution Approach 1:
The patent enables direct stacking alignment by moving the electrical connection interface to the lateral surface of the MEMS die. Conductive vias penetrate through the MEMS die thickness, and bonding pads are formed on the side surface, allowing vertical stacking without requiring lateral offset or staggering for pad exposure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise electrical connections without mechanical stress, reducing the need for wire bonding and enabling smaller form factors by moving electrical contacts to the periphery, thus minimizing resonance frequency impacts and eliminating the need for bonding pads.
Implementation Method 1
forming a monolithic wafer by stacking the CMOS wafer and the MEMS wafer... eutectic bonding the CMOS wafer to the MEMS wafer
Data Source
AI summary
A device includes a first die and a second die. The first die and the second die are stacked and form a monolithic die. A first side of the first die faces a first side of the second die. The second die comprises an electrical connection within its periphery and on a side other than the first side of the second die. The electrical connection exposes the second die to an environment outside of the monolithic die. The electrical connection is configured to facilitate electrical connection between the second die of the monolithic die and an electronic component that is external to the monolithic die.