MEMS CMOS Integration via Embedded Conductive Dielectric Etching

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Solution Overview

Problem

Current MEMS devices are not easily integrated into standard MOS processes, such as CMOS, due to compatibility issues, leading to higher costs and performance limitations.

Innovation Solution

A method for fabricating MEMS devices that involves forming a structural dielectric layer with an embedded conductive layer on a substrate, followed by a multi-stage patterning process and isotropic etching to create regions with different levels, allowing for integration with CMOS devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If MEMS devices are fabricated using discrete packaging with CMOS ASIC chips, then device functionality is achieved, but manufacturing cost increases and integration density decreases

Engineering Contradiction:

Improvemanufacturing costVSAvoidintegration process complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent merges MEMS fabrication processes with standard CMOS manufacturing processes, allowing both MEMS devices and CMOS circuits to be fabricated simultaneously on the same substrate using compatible process steps such as deposition, etching, and doping, thereby eliminating discrete packaging and reducing manufacturing cost

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent develops a universal fabrication process that can manufacture both CMOS electronic devices and MEMS mechanical devices using the same semiconductor manufacturing line and process techniques, enabling single-chip integration and improving manufacturing efficiency

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If MEMS devices are packaged separately from CMOS chips, then device functionality is maintained, but integration density and performance are limited

Engineering Contradiction:

Improveintegration densityVSAvoiddevice performance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent combines MEMS structures and CMOS circuits into a single integrated device on the same substrate, allowing direct electrical and mechanical interconnections without external packaging, thereby increasing integration density and improving device performance through reduced parasitic effects and shorter interconnect lengths

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If multi-stage patterning and isotropic etching are used to create multi-level regions, then substrate regions with different levels are formed for integration, but process complexity increases

Engineering Contradiction:

Improvesubstrate structure flexibilityVSAvoidfabrication process steps

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the substrate into multiple regions with different levels by selectively patterning and etching different areas, creating distinct zones for CMOS devices, MEMS devices, and interconnection structures that can be independently optimized for their specific functions

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates three-dimensional multi-level structures on the substrate by forming regions at different heights through controlled etching processes, enabling vertical stacking and three-dimensional integration of CMOS and MEMS components to increase device density

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables compact integration of MEMS devices with CMOS devices, reducing costs and improving performance by using semiconductor fabrication processes compatible with CMOS technology.

Implementation Method 1

An isotropic etching process is performed from the second side of the substrate or from the both side of the substrate to etch the structural dielectric layer

Methodology Applied

Scientific EffectIsotropic etching:

Data Source

PatentUS8173471B2Method for fabricating micro-electro-mechanical system (MEMS) device

Publication Date: 2012.05.08 SOLID STATE SYST

AI summary

A method for fabricating MEMS device includes providing a substrate having a first side and a second side. Then, a structural dielectric layer is formed over the substrate at the first side, wherein a structural conductive layer is embedded in the structural dielectric layer. A multi-stage patterning process is performed on the substrate from the second side, wherein a plurality of regions of the substrate with different levels is formed and a portion of the structural dielectric layer is exposed. An isotropic etching process is performed from the second side of the substrate or from the both side of the substrate to etch the structural dielectric layer, wherein a remaining portion of the structural dielectric layer comprises the structural conductive layer and a dielectric portion enclosed by the structural conductive layer.