MEMS CMOS Integration via Monolithic BEOL Interconnects
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Solution Overview
Problem
Current methods for packaging microelectromechanical systems (MEMS) devices with complementary metal-oxide-semiconductor (CMOS) devices result in high parasitic capacitance, complex packaging processes, and high costs due to wire bonding and the use of sacrificial layers, which can be damaged by high temperatures.
Innovation Solution
A method involving the formation of a BEOL interconnect structure with a dielectric stack, a lateral etch to create a trench, and a piezoelectric layer over a semiconductor substrate, allowing for electrical coupling of MEMS devices to CMOS devices without wire bonding, performed at the wafer level to reduce packaging time and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to electrically couple MEMS devices to CMOS devices, then electrical connection is achieved, but parasitic capacitance increases and packaging complexity increases
Solution Approach 1:
The patent merges the MEMS device fabrication and CMOS device fabrication into a single integrated process on the same substrate. The MEMS cavity is formed within the CMOS substrate, and interconnect structures are formed to electrically couple MEMS elements directly to CMOS circuitry, eliminating the need for separate wire bonding operations and reducing packaging complexity.
Solution Approach 2:
The patent performs preliminary actions by forming the MEMS cavity, sacrificial layers, and interconnect structures during the CMOS fabrication process itself, before final device completion. This preliminary integration of MEMS structures into the CMOS substrate eliminates subsequent wire bonding steps and reduces overall packaging complexity.
2Ease of manufacture
If sacrificial layers are used in MEMS fabrication, then cavity formation is enabled, but the layers can be damaged by high temperatures
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary material that temporarily occupies the space where the MEMS cavity will eventually be. This sacrificial layer enables cavity formation through selective removal, while the patent addresses its temperature sensitivity by carefully controlling processing temperatures or using temperature-resistant sacrificial materials that can withstand CMOS fabrication thermal cycles.
3Adaptability or versatility
If traditional packaging methods are used for MEMS and CMOS devices, then device integration is achieved, but packaging time increases and costs increase
Solution Approach 1:
The patent combines MEMS device fabrication and CMOS device fabrication into a single unified process flow on the same substrate. This merging of fabrication processes eliminates separate packaging operations, reduces packaging time, and lowers overall manufacturing costs while achieving tight integration between MEMS and CMOS devices.
Solution Approach 2:
The patent segments the substrate into distinct regions for CMOS circuitry and MEMS structures, allowing parallel fabrication of both device types using standardized CMOS processes. This segmentation enables high-volume manufacturing with improved productivity while maintaining the versatility of integrating different device functions on a single chip.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, lowers packaging costs, and avoids damage to sensitive layers by using a monolithic process that does not rely on wire bonding or sacrificial layers, enabling efficient integration of MEMS and CMOS devices with improved performance.
Implementation Method 1
a piezoelectric layer over a semiconductor substrate
Data Source
AI summary
Processes for integrating complementary metal-oxide-semiconductor (CMOS) devices with microelectromechanical systems (MEMS) devices are provided. In some embodiments, the MEMS devices are formed on a sacrificial substrate or wafer, the sacrificial substrate or wafer is bonded to a CMOS die or wafer, and the sacrificial substrate or wafer is removed. In other embodiments, the MEMS devices are formed over a sacrificial region of a CMOS die or wafer and the sacrificial region is subsequently removed. Integrated circuit (ICs) resulting from the processes are also provided.