MEMS CMOS Packaging Via Structures
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Solution Overview
Problem
Conventional MEMS and IC packaging technologies face challenges in efficiently utilizing space due to large spatial regions between bonding pads and MEMS devices, leading to inefficiencies in area usage and difficulties in wire bonding processes.
Innovation Solution
The proposed solution involves a packaging apparatus that includes a semiconductor substrate with MEMS devices overlying an inner region, an enclosure housing the MEMS devices, and bonding structures with pads and via structures to facilitate efficient bonding and minimize spatial obstructions, allowing for more compact and efficient integration of MEMS and ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional MEMS and IC packaging technologies are used, then device functionality is achieved, but spatial efficiency deteriorates due to large spatial regions between bonding pads and MEMS devices
Solution Approach 1:
The patent merges the bonding pad structure with the MEMS device structure by integrating via structures directly into the MEMS device substrate. This consolidation eliminates the need for separate bonding pad regions and reduces the spatial distance between bonding pads and MEMS devices, thereby improving spatial efficiency while maintaining functional integrity.
Solution Approach 2:
The patent utilizes vertical via structures to establish electrical connections in the vertical dimension rather than relying solely on horizontal trace routing. By moving connections into the vertical dimension through via holes, the design reduces the horizontal footprint and minimizes the spatial region between bonding pads and MEMS devices.
2Ease of operation
If large spatial regions are maintained between bonding pads and MEMS devices, then wire bonding accessibility is improved, but area utilization deteriorates
Solution Approach 1:
The patent applies local quality by providing via structures at specific locations within the MEMS device substrate where electrical connections are needed, rather than maintaining uniform large spatial regions throughout. This localized approach to connectivity maintains wire bonding accessibility at critical points while minimizing overall area consumption.
Solution Approach 2:
The via structures serve as intermediary elements that facilitate electrical connections between bonding pads and MEMS devices without requiring large open spatial regions. These via structures act as mediators that enable compact routing while maintaining bonding accessibility through optimized via placement and dimensions.
3Productivity
If conventional packaging approaches are used, then manufacturing simplicity is maintained, but device yields deteriorate due to parasitic resistances and capacitances
Solution Approach 1:
The patent extracts and eliminates the parasitic elements associated with long trace routing by directly connecting bonding pads to MEMS devices through via structures. By removing the intermediate trace routing path, the design reduces parasitic resistances and capacitances, thereby improving device yields and reliability.
Solution Approach 2:
The via structures are integrated into the MEMS device substrate during the fabrication process itself, establishing low-parasitic electrical connections before final packaging. This preliminary integration of connection structures during manufacturing ensures minimal parasitic elements are present from the outset, improving device yields without requiring additional post-fabrication steps.
Data Source
AI summary
An apparatus for packaging MEMS and ICs can include a semiconductor substrate, one or more MEMS devices, an enclosure, and one or more bonding structures. The semiconductor substrate can be bonded to a portion of the surface region. The semiconductor substrate can include one or more integrated circuits. Also, the semiconductor substrate can have an upper surface region. The one or more MEMS devise can overlie an inner region of the upper surface region formed by the semiconductor substrate. The enclosure can house the one or more MEMS devices. The enclosure can overlie a first outer region of the upper surface region. Also, the enclosure can have an upper cover region. The one or more bonding structures can be provided within a second outer region of the supper surface region.