MEMS-CMOS Integration Plasma Damage Protection
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Solution Overview
Problem
Conventional MEMS devices face challenges such as Plasma Induced Damage (PID) during etching processes, uneven stress distribution leading to performance variations, and stiction issues, which affect the reliability and accuracy of inertial sensors and other MEMS components.
Innovation Solution
The integration of a protection structure within the MEMS layer, including ground posts, jumpers, and ESD diodes, which provides an alternate path for CMOS circuits during etching and reduces differential bias and stiction through symmetric electrode configurations and staggered serpentine spring structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used during MEMS fabrication, then the MEMS structures can be formed, but Plasma Induced Damage occurs to the underlying CMOS circuits
Solution Approach 1:
A plasma protection structure is introduced as an intermediary element between the MEMS layer and CMOS circuits. This structure includes plasma protection patterns formed in the MEMS layer that act as a shield during plasma etching processes, preventing harmful plasma exposure to the CMOS circuits below while allowing the etching to proceed for MEMS structure formation.
Solution Approach 2:
The plasma protection structure is formed in advance before the plasma etching process. The protection patterns are created during earlier fabrication steps, establishing a protective barrier that prevents Plasma Induced Damage before the damaging plasma exposure occurs during subsequent etching operations.
2Ease of manufacture
If asymmetric substrate stress distribution exists in MEMS devices, then device fabrication is simplified, but differential bias increases reducing sensor accuracy
Solution Approach 1:
The patent intentionally introduces asymmetric dummy regions with different stress characteristics to counterbalance the inherent asymmetric stress in the MEMS structure. By strategically placing dummy structures with opposite stress signs, the net stress distribution becomes more uniform, reducing differential bias while maintaining the simplicity of the overall fabrication process.
3Device complexity
If standard spring structures are used in MEMS devices, then device complexity is reduced, but stiction issues increase affecting component reliability
Solution Approach 1:
The patent modifies the spring structure by introducing curved or serpentine geometries instead of straight linear springs. This curvature increases the surface area and distributes contact forces more evenly, reducing stiction between adjacent components while maintaining relatively simple fabrication processes. The serpentine pattern allows the spring to flex more effectively without creating high-stress concentration points.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively protects CMOS circuits from plasma damage, balances stress distribution, and reduces stiction, resulting in improved reliability and accuracy of MEMS devices by integrating a protection structure and using symmetric designs.
Implementation Method 1
During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID).
Implementation Method 2
bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE)
Data Source
AI summary
A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.