MEMS-CMOS Shielding Layer for Plasma Damage Prevention
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Solution Overview
Problem
Conventional MEMS fabrication processes, such as Deep Reactive Ion Etching (DRIE), often cause Plasma Induced Damage (PID) to CMOS circuits due to exposure during the etching of mechanical layers, leading to structural damage and leakage issues.
Innovation Solution
A method involving the use of a shielding layer grounded to prevent charging and an isolative path is implemented, where a bottom isolation layer is formed between the CMOS IC layer and the shielding layer, and a top isolation layer is formed over the shielding layer, allowing for the etching of the MEMS layer without damaging the CMOS circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If DRIE process is used to etch MEMS mechanical layer, then MEMS structure fabrication is achieved, but Plasma Induced Damage occurs to CMOS circuits
Solution Approach 1:
A shielding layer is introduced as an intermediary component between the MEMS mechanical layer and the CMOS circuit layer. This shielding layer acts as a mediator that blocks plasma-induced damage from reaching the CMOS circuits while allowing the DRIE process to successfully etch the MEMS structures above it.
Solution Approach 2:
The device structure is segmented into distinct functional layers: a bottom isolation layer, a shielding layer, a top isolation layer, and a MEMS mechanical layer. This segmentation allows each layer to serve its specific function - the shielding layer protects CMOS circuits, while the isolation layers provide electrical separation and structural support.
2Reliability
If shielding layer is added to protect CMOS circuits, then PID is prevented, but device complexity increases
Solution Approach 1:
The shielding layer serves multiple functions simultaneously: it shields CMOS circuits from plasma damage, provides an etch stop layer to control etching depth, and acts as a structural support for the MEMS mechanical layer. This multi-functionality reduces the need for additional separate components.
Solution Approach 2:
The bottom isolation layer and shielding layer are merged into a single integrated structure that provides both electrical isolation and plasma protection functions, simplifying the overall device architecture while maintaining all necessary protective functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively protects CMOS circuits from PID and leakage, enabling the integration of MEMS and CMOS devices on a single die while being compatible with conventional semiconductor and MEMS process technologies without significant equipment or process modifications.
Implementation Method 1
etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE)
Implementation Method 2
A bottom isolation layer can be formed overlying the CMOS IC layer and a shielding layer and a top isolation layer can be formed overlying a portion of bottom isolation layer
Data Source
AI summary
A method for fabricating an integrated MEMS-CMOS device. The method can include providing a substrate member having a surface region and forming a CMOS IC layer having at least one CMOS device overlying the surface region. A bottom isolation layer can be formed overlying the CMOS IC layer and a shielding layer and a top isolation layer can be formed overlying a portion of bottom isolation layer. The bottom isolation layer can include an isolation region between the top isolation layer and the shielding layer. A MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer, and can be etched to form at least one MEMS structure having at least one movable structure and at least one anchored structure.