MEMS Device Stacked on CMOS Circuit for RF Filter Integration
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Solution Overview
Problem
Current manufacturing technologies for RF MEMS film bulk acoustic wave filters face challenges with complex processes, low integration density, and thermal limitations, particularly in achieving precise signal transmission and integration of IC circuits and film bulk acoustic wave filters on a single chip.
Innovation Solution
A manufacturing method involving the formation of a stacked piezoelectric layer, a sacrificial layer, and a through hole to create a cavity without deforming it, allowing for a simplified process and reduced chip size by stacking the MEMS module on the CMOS circuit, eliminating the need for eutectic bonding and enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SIP packaging is used to integrate filter, driving circuit and processing circuit, then integration is achieved, but interconnection length increases and integration density decreases
Solution Approach 1:
The patent merges the filter structure and IC circuit into a single integrated device where the IC circuit is formed within the filter body. The driving circuit and processing circuit are directly integrated with the filter structure, eliminating the need for separate packaging and long interconnections. This is achieved by forming the IC circuit in the same substrate as the filter, with electrodes directly connected to the piezoelectric layer.
Solution Approach 2:
The patent transitions from a planar two-dimensional integration approach to a three-dimensional vertical integration structure. The IC circuit is embedded within the filter body, with components arranged in multiple layers vertically. This dimensional change allows for shorter interconnections and higher integration density by utilizing the vertical space within the filter structure.
2Area of stationary object
If two-dimensional planar structure is used to integrate IC circuit and film bulk acoustic wave filter, then chip size is reduced, but process complexity increases and flexibility decreases
Solution Approach 1:
The patent employs three-dimensional vertical integration instead of two-dimensional planar integration. The IC circuit is formed within the bulk of the filter structure, with electrodes, piezoelectric layers, and circuit components arranged in vertical layers. This approach reduces chip size while simplifying the manufacturing process by using standard semiconductor fabrication techniques rather than complex planar integration methods.
Solution Approach 2:
The patent implements a nested structure where the IC circuit is embedded within the filter body. The electrodes are formed within the filter structure, the piezoelectric layer is deposited on the electrodes, and the IC circuit components are integrated within the same substrate. This nested arrangement reduces the overall chip size while maintaining process simplicity through sequential fabrication steps.
3Ease of manufacture
If cavity is formed before forming stacked piezoelectric layer, then cavity formation is simplified, but cavity deformation occurs due to piezoelectric layer formation
Solution Approach 1:
The patent applies preliminary action by forming the cavity structure with sacrificial materials before depositing the piezoelectric layer. The sacrificial layer is formed in the cavity region, then the piezoelectric layer is deposited over it. After deposition, the sacrificial material is removed, leaving a precisely formed cavity. This preliminary structuring prevents cavity deformation during piezoelectric layer formation while maintaining manufacturing simplicity.
Solution Approach 2:
The patent uses sacrificial materials as intermediary substances during the fabrication process. These sacrificial layers are deposited in the cavity regions, serve as placeholders during piezoelectric layer formation, and are subsequently removed to create the final cavity structure. This intermediary approach allows the cavity to maintain its shape during subsequent processing steps while simplifying the overall manufacturing sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process, reduces costs and chip size, improves signal precision, and increases device reliability by enabling a high-sensitivity film bulk acoustic wave filter with reduced power consumption and package pins.
Implementation Method 1
forming a piezoelectric layer on the first electrode and above the sacrificial layer
Data Source
AI summary
A MEMS device and a manufacturing method thereof. The manufacturing method comprises: forming a CMOS circuit; and forming a MEMS module on the CMOS circuit which is coupling to the MEMS module and configured to drive the MEMS module. Forming the MEMS module comprises: forming a protective layer; forming a sacrificial layer in the protective layer; forming a first electrode on the protective layer and on the sacrificial layer so that the first electrode covers the sacrificial layer, and electrically coupling the first electrode to the CMOS circuit; forming a piezoelectric layer on the first electrode and above the sacrificial layer; forming a second electrode on the piezoelectric layer and electrically coupling the second electrode to the CMOS circuit; forming a through hole to reach the sacrificial layer; and forming a cavity by removing the sacrificial layer through the through hole.