Wafer-Level MEMS-CMOS Integration via Fusion Bonding

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Solution Overview

Problem

Current CMOS-MEMS integration at the chip level is limited by the maximum temperature of metal components in the CMOS substrate, typically less than 450°C, and results in undesired high parasitic capacitance.

Innovation Solution

The integration of MEMS and CMOS devices is performed at the wafer level by bonding a first wafer with a MEMS device layer, composed of high-temperature resistant semiconductor materials like polysilicon and single crystal silicon, with a second wafer containing CMOS devices, using fusion bonding or eutectic bonding techniques, allowing for low or no parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If CMOS-MEMS integration is performed at chip level, then device performance is improved and packaging size is reduced, but the integration is limited by maximum temperature of metal components (typically less than 450°C)

Engineering Contradiction:

Improvedevice performanceVSAvoidmaximum temperature of metal components

Core Design Contradiction:

ReliabilityVSTemperature

Solution Approach 1:

The patent segments the integration process into two separate wafers: a first wafer for MEMS device fabrication using high-temperature resistant materials (polysilicon, single crystal silicon), and a second wafer for CMOS device fabrication. This segmentation allows each wafer to be processed independently at appropriate temperatures before bonding, thereby resolving the temperature limitation constraint while maintaining device performance.

Inventive Principle:

Principle #1Segmentation

2Area of stationary object

If CMOS-MEMS integration is performed at chip level, then packaging size is reduced, but undesired high parasitic capacitance is generated

Engineering Contradiction:

Improvepackaging sizeVSAvoidparasitic capacitance

Core Design Contradiction:

Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the parasitic capacitance problem by using high-temperature resistant semiconductor materials (polysilicon, single crystal silicon) for MEMS device fabrication on a separate wafer before bonding. These materials inherently produce lower parasitic capacitance compared to metal-based implementations, thereby eliminating the harmful effect while maintaining compact packaging size through wafer-level integration.

Inventive Principle:

Principle #2Taking out (Extraction)

3Temperature

If high-temperature resistant semiconductor materials like polysilicon and single crystal silicon are used for MEMS device layer, then temperature limitations are removed, but manufacturing complexity increases

Engineering Contradiction:

Improvetemperature resistanceVSAvoidmanufacturing complexity

Core Design Contradiction:

TemperatureVSDevice complexity

Solution Approach 1:

The patent divides the manufacturing process into separate stages for different materials: the first wafer is dedicated to MEMS device fabrication using high-temperature resistant materials (polysilicon, single crystal silicon), while the second wafer handles CMOS devices. This segmentation allows each process to be optimized independently, managing manufacturing complexity through modular fabrication and bonding procedures.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the formation of CMOS-MEMS integrated devices without temperature limitations and reduces parasitic capacitance, facilitating the integration of various MEMS structures with CMOS devices.

Implementation Method 1

bonding a first wafer with a MEMS device layer, composed of high-temperature resistant semiconductor materials like polysilicon and single crystal silicon, with a second wafer containing CMOS devices, using fusion bonding or eutectic bonding techniques

Methodology Applied

Scientific EffectFusion bonding: Welding

Implementation Method 2

Methodology Applied

Scientific EffectEutectic bonding: Soldering

Data Source

PatentUS9309109B2MEMS-CMOS integrated devices, and methods of integration at wafer level

Publication Date: 2016.04.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method for forming an integrated semiconductor device includes providing a first wafer, providing a second wafer, and bonding the first wafer over the second wafer. The first wafer includes a first substrate having a microelectromechanical system (MEMS) device layer. The second wafer includes a second substrate having at least one active device, and at least one interconnect layer over the second substrate. The MEMS device layer is connected with the at least one interconnect layer. The method further includes forming at least one conductive plug through the first substrate and the MEMS device layer and inside the at least one interconnect layer, etching the second substrate and the at least one interconnect layer to form a cavity extending from a surface of the second substrate to the MEMS device layer, and etching the first substrate and the MEMS device layer to form a MEMS device interfacing with the cavity.