Wafer Level MEMS Packaging with Hybrid Bonding and Pressurized Cavity
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Solution Overview
Problem
Current wafer-level chip scale packaging technologies, such as bulk WLCSP and surface WLCSP, face challenges including high costs due to deep silicon etching and reliability issues like void formation and delamination, particularly when attempting to create electrical connections across thick chip scale packaging layers.
Innovation Solution
The proposed solution involves a hybrid surface-bulk WLCSP technology that uses a silicon substrate with closed ring pads and a silicon cap wafer, forming hermetic seal rings and electrical connections through eutectic or metal diffusion bonding, with a pressurized gaseous species in the gap between the substrate and cap wafer, and conductive material-filled TSVs, allowing connections to be formed over and through the packaging layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep silicon etching is used to form TSVs for electrical connections through thick substrates, then electrical connectivity is achieved, but manufacturing cost increases and void formation occurs
Solution Approach 1:
The patent divides the electrical connection path into two segments: TSVs formed only in the cap wafer (not through the entire substrate) and bond wires connecting from substrate surface pads to TSV contacts. This segmentation avoids the need for deep through-substrate etching, reducing manufacturing cost and void formation while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from a purely vertical through-substrate connection approach to a hybrid approach that combines partial vertical TSVs in the cap wafer with lateral bond wire connections from the substrate surface. This dimensional change allows electrical connections without requiring deep etching through the entire substrate thickness.
2Length of stationary object
If TSV trenches are made deeper to connect through thicker substrates, then electrical connectivity improves, but void formation increases
Solution Approach 1:
The patent segments the connection path so that TSVs are formed only in the cap wafer to a controlled depth, while the remaining connection distance is covered by bond wires from the substrate surface. This prevents the need for deep TSVs that would cause voids in thicker substrates.
Solution Approach 2:
The patent introduces bond wires as an intermediary connection element that bridges the gap between substrate surface pads and TSV contacts in the cap wafer. This intermediary allows electrical connection through thick substrates without requiring proportionally deeper TSVs that would create voids.
3Reliability
If conductors run over the top of the packaging layer, then electrical connections are achieved, but delamination occurs
Solution Approach 1:
The patent segments the conductor path into TSVs embedded within the cap wafer bulk and separate bond wires connected to substrate surface pads. This segmentation keeps conductors away from the cap wafer top surface, eliminating the delamination issue while maintaining electrical connection functionality.
4Area of stationary object
If the footprint of active area is reduced, then device integration improves, but electrical connection formation becomes more difficult
Solution Approach 1:
The patent uses bond wires to extend electrical connections from substrate surface pads to cap wafer TSV contacts in the vertical dimension, rather than requiring extended lateral conductor traces on the substrate surface. This allows reduced active area footprint while maintaining connection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the footprint of the active area, decreases costs, and enhances reliability by providing robust electrical connections across thick chip scale packaging layers, minimizing voids and delamination issues.
Implementation Method 1
forming hermetic seal rings by a bonding between said at least one closed ring pad formed on said substrate and said at least one closed ring pad formed on said cap wafer
Implementation Method 2
forming hermetic seal rings by a bonding between said at least one closed ring pad formed on said substrate and said at least one closed ring pad formed on said cap wafer (such as eutectic or metal diffusion bonding)
Implementation Method 3
wherein said gap is filled with a pressurized gaseous species
Implementation Method 4
conductive material-filled TSVs, allowing connections to be formed over and through the packaging layer
Data Source
AI summary
Packaged MEMS devices are described. One such device includes a substrate having an active surface with an integrated circuit. Two substrate pads are formed on the substrate; one pad is a closed ring pad. The device also includes a cap wafer with two wafer pads. One of these wafer pads is also a closed ring pad. A hermetic seal ring is formed by a first bonding between the two ring pads. The device has a gap between the substrate and the cap wafer. This gap may be filled with a pressurized gas. An electrical connection is formed by a second bonding between one substrate pad and one wafer pad. An electrical contact is disposed over the cap wafer. The device also includes an insulation layer between the electrical contact and the cap wafer. Methods of producing the packaged MEMS devices are also described.