MEMS Logic Gate Circuit for Low-Loss RF Switch Control
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Solution Overview
Problem
Current MEMS switches face challenges in efficiently integrating with semiconductor substrates to form miniature circuits for digital logic functions, particularly in radio frequency applications, due to limitations in reducing insertion losses and parasitic capacitance and inductance compared to silicon-on-insulator complementary metal oxide switches.
Innovation Solution
A microelectromechanical systems (MEMS) logic gate is developed, comprising first and second logic MEMS switches with internal logic gate circuitry, integrated within a MEMS switch die, utilizing a MEMS-based decoder to decode signals and control RF MEMS switches, reducing the number of control lines required by using a charge pump to generate gate driving voltages and incorporating shunt MEMS switches for improved isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If MEMS switches are used to replace FETs in signal paths, then insertion losses are reduced, but device complexity increases due to integration requirements
Solution Approach 1:
The patent combines multiple MEMS switches and logic gate circuitry into a single integrated MEMS logic gate device. This merging approach reduces the number of discrete components and interconnections required, thereby reducing overall device complexity while maintaining the low insertion loss benefits of MEMS switches.
Solution Approach 2:
The MEMS logic gate integrates multiple functions including switching, logic operations, and control signal generation within a single device. This multi-functionality eliminates the need for separate control circuits and reduces the overall system complexity while preserving the energy efficiency advantages of MEMS technology.
2Reliability
If MEMS switches are used in RF applications, then linearity is improved, but parasitic capacitance and inductance remain problematic
Solution Approach 1:
The patent employs parameter changes in the MEMS switch design, including optimizing beam dimensions, material properties, and electrostatic control parameters to minimize parasitic capacitance and inductance. By carefully adjusting these parameters, the device maintains high linearity while reducing harmful parasitic effects.
3Productivity
If multiple RF MEMS switches are integrated on a single die, then productivity is improved, but control line requirements increase
Solution Approach 1:
The MEMS-based decoder circuit is designed to control multiple RF MEMS switches using a reduced set of control lines. The decoder efficiently encodes and decodes control signals, allowing a single control line to manage multiple switches through time-multiplexed or code-based control schemes, thereby reducing the overall control line requirements.
4Object-generated harmful factors
If MEMS switches replace FETs, then parasitic inductance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes manufacturing parameters including beam thickness, gap dimensions, and material composition to achieve the desired low parasitic inductance performance. By carefully controlling these parameters within practical fabrication tolerances, the device achieves minimal parasitic inductance without requiring excessively tight manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MEMS logic gate effectively reduces the number of control lines needed for RF MEMS switches, enhances isolation, and improves the efficiency of signal switching by electrostatically controlling the MEMS switches, addressing the limitations of existing technologies in reducing insertion losses and parasitic effects.
Implementation Method 1
the higher gate voltage electrostatically pulls the RF beam and brings the RF switch contact into electrical contact with the RF terminal contact
Data Source
AI summary
Disclosed is a microelectromechanical systems (MEMS) logic gate with a first logic MEMS switch having a first beam with a first switch contact, a first gate, and a first terminal contact, wherein the first beam is coupled to a fixed higher voltage node. The MEMS logic gate also includes a second logic MEMS switch having a second beam with a second switch contact, a second gate, and a second terminal contact, wherein the second beam is electrically coupled to a fixed lower voltage node. Further included is internal logic gate circuitry having a first input terminal and a first output terminal, wherein the internal logic gate circuitry is electrically coupled between the first terminal contact of the first logic MEMS switch and the second terminal contact of the second logic MEMS switch.