Wafer-Level MEMS Microphone Packaging for Cost and Size Reduction
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Solution Overview
Problem
Conventional MEMS microphone packaging is cost-ineffective, limits manufacturability and performance consistency, and restricts size reduction due to its incompact structure and high packaging costs, especially for smaller sizes.
Innovation Solution
A fully wafer-level-packaging technique for silicon-based MEMS microphones, involving separate manufacturing of packaging and MEMS microphone wafers, followed by wafer-to-wafer bonding and singulation to create fully packaged units with electrical connections, which are then aligned and bonded using metal-metal, metal eutectic, or conductive adhesive bonding, ensuring surface mountability without further processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MEMS microphone packaging is used, then the microphone can be packaged and tested, but packaging cost becomes a major portion of total cost and limits cost-effectiveness
Solution Approach 1:
The patent merges the MEMS microphone chip manufacturing with the packaging process by performing wafer-level packaging. Multiple chips are packaged simultaneously on the wafer level rather than individually, combining what were previously separate processes into one integrated flow, thereby reducing packaging cost which becomes a minor portion of total cost
Solution Approach 2:
The patent performs packaging actions before die singulation. The packaging structure is formed over the entire wafer, and only after packaging is complete are the individual chips separated. This preliminary packaging action enables cost-effective mass production while ensuring each chip receives proper packaging protection
2Ease of manufacture
If conventional packaging is used, then individual chips can be packaged, but separate packaging of singulated chips limits manufacturability and mass production efficiency
Solution Approach 1:
The patent combines chip packaging with wafer-level processing by performing packaging operations on the entire wafer before singulation. This merging of processes allows all chips to be packaged simultaneously in one batch operation, dramatically improving productivity and mass production efficiency compared to individual chip packaging
Solution Approach 2:
The packaging structure is formed preliminarily over the complete wafer before the chips are separated. This preliminary action at the wafer level enables efficient batch processing, where packaging, curing, and structural formation are completed for all chips simultaneously, then singulation separates them into individual packaged units
3Ease of manufacture
If conventional packaging processes are used, then chips can be packaged, but particle and organic contaminations are not easily prevented, affecting performance consistency
Solution Approach 1:
The patent performs wafer-level packaging in a controlled cleanroom environment that maintains inert conditions throughout the process. By keeping all chips packaged simultaneously in a controlled atmosphere from the start, particle and organic contaminations are prevented from entering the packaging structure, ensuring consistent performance across all chips
Solution Approach 2:
The patent merges the packaging process with the wafer fabrication process, performing both in a continuous controlled environment. This integration ensures that chips are packaged immediately after processing without exposure to contaminated environments, preventing contamination and maintaining performance consistency
4Ease of operation
If conventional packaging structure is used, then surface mountable components can be housed, but the incompact structure highly limits size reduction
Solution Approach 1:
The patent implements a nested structure where the acoustic cavity, acoustic sensing part, and packaging layers are arranged in compact concentric or layered configurations. The packaging structure is formed directly over the chip surface with minimal spacing, nesting multiple functional elements within a small footprint while maintaining surface mountability
Solution Approach 2:
The patent transitions from planar packaging layouts to three-dimensional stacked configurations. By utilizing vertical spacing and layered structures, the packaging achieves compact size in the horizontal plane while accommodating all necessary acoustic and electrical functions through vertical arrangement, enabling significant size reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances cost-effectiveness, performance consistency, and manufacturability, reduces packaging costs, and allows for smaller package sizes while minimizing yield loss and contamination risks, ensuring mechanical robustness and compliance with customer specifications.
Implementation Method 1
performing wafer-to-wafer bonding for the MEMS microphone wafer and the first packaging wafer and for the second packaging wafer and the MEMS microphone wafer... bonded using metal-metal, metal eutectic, or conductive adhesive bonding
Implementation Method 2
bonded using metal-metal, metal eutectic, or conductive adhesive bonding
Data Source
AI summary
The present invention provides a method for manufacturing a fully wafer-level-packaged MEMS microphone and a microphone manufactured with the same, the method comprises: separately manufacturing a first packaging wafer, an MEMS microphone wafer and a second packaging wafer; performing wafer-to-wafer bonding for the three wafers to form a plurality of fully wafer-level-packaged MEMS microphone units; singulating the fully wafer-level-packaged MEMS microphone units to form a plurality of fully wafer-level-packaged MEMS microphones, which are fully packaged at wafer level and do not need any further process after die singulation. The method can improve cost-effectiveness, performance consistency, manufacturability, quality, scaling capability of the packaged MEMS microphone.


