MEMS Microphone VCO-ADC Clock Jitter for Idle Tone Mitigation
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Solution Overview
Problem
Challenges exist in using voltage-controlled-oscillator-based ADCs (VCO-ADCs) in MEMS microphone systems, particularly in suppressing audible whistles caused by low frequency tones during mechanical shocks or strong audio signals, which conventional dithering solutions compromise sensitivity and dynamic range.
Innovation Solution
A MEMS microphone system incorporating a VCO-ADC with a random number generator and phase modulator that modulates the phase of the system sampling clock signal with random numbers, allowing the FTD converter to generate a digital output signal by sampling with a phase modulated clock signal, thereby decorrelating the sweeping VCO frequency and randomizing whistles as noise without affecting sensitivity or dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional dithering solutions are used to suppress audible whistles, then whistle suppression is improved, but sensitivity and dynamic range deteriorate
Solution Approach 1:
The patent changes the parameter of the sampling clock signal by introducing random phase delays (jitter) to decorrelate the sweeping VCO frequency from the sampling clock, thereby randomizing whistles as noise without affecting the sensitivity or dynamic range of the microphone system
Solution Approach 2:
The patent introduces an intermediary element (random phase delay generator) that modifies the sampling clock signal phase to break the correlation between the VCO frequency sweep and sampling clock, converting coherent whistles into incoherent noise while preserving signal integrity
2Object-affected harmful factors
If additional circuits are added to suppress whistles, then whistle suppression is improved, but device complexity and production cost increase
Solution Approach 1:
The patent merges the whistle suppression function into the existing sampling clock signal path by introducing random phase delays, eliminating the need for separate additional circuits and reducing overall device complexity while maintaining production cost efficiency
3Object-affected harmful factors
If additional circuits are added to suppress whistles, then whistle suppression is improved, but energy consumption increases
Solution Approach 1:
The patent combines the whistle suppression functionality with the existing sampling clock generation circuitry, using the same clock signal path with added random phase delays, thereby avoiding additional energy-consuming circuits while achieving effective whistle suppression
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses audible whistles by introducing random phase delays in the sampling process, reducing noise peaks and maintaining the microphone's performance without the need for additional circuits, thus saving production costs and energy.
Implementation Method 1
a phase modulator configured to generate a phase modulated clock signal by modulating a phase of a system sampling clock signal with the random numbers
Data Source
AI summary
A circuit includes: a capacitive micro-electromechanical system (MEMS) microphone configured to generate a voltage signal in response to a sound signal; a voltage-controlled oscillator (VCO) coupled to the capacitive MEMS microphone, where the VCO is configured to generate a frequency modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital (FTD) converter coupled to an output terminal of the VCO; a random number generator configured to generate random numbers; and a phase modulator configured to generate a phase modulated clock signal by modulating a phase of a system sampling clock signal in accordance with the random numbers, where the FTD converter is configured to generate a digital signal in accordance with the frequency modulated signal and the phase modulated clock signal, and is configured to sample the digital signal by the phase modulated clock signal to generate a digital output signal of the FTD converter.