MEMS Microphone Clock Switching Without Restart Artefacts
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Solution Overview
Problem
Existing digital microphones face challenges in seamlessly adjusting between operating modes without restart delays and minimizing switching artefacts during transitions between low power and high performance modes.
Innovation Solution
A digital microphone design that allows for seamless mode transitions by using a clock divider and multiplexer to adjust internal clock rates in response to an external control signal, with a repeater to maintain a constant output signal clock rate and minimize switching artefacts, and optionally adjusting filter coefficients for optimal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the internal clock rate is changed to adjust between low power and high performance modes, then power consumption is reduced or performance is improved, but restart delays and switching artefacts occur during mode transitions
Solution Approach 1:
The system performs preliminary actions by pre-configuring the clock divider and multiplexer to enable seamless clock rate transitions. The repeater is prepared in advance to buffer and retransmit data at the appropriate clock rate, allowing mode switching without restart delays. Filter coefficients are pre-calculated and ready for immediate switching when mode changes occur.
Solution Approach 2:
The repeater acts as an intermediary component between the ADC and the output stage. It receives data at one clock rate and retransmits it at another clock rate, mediating the transition between low power and high performance modes. This intermediary buffer eliminates the need for system restart during mode changes and reduces switching artefacts.
2Adaptability or versatility
If the internal clock rate is changed to adjust between low power and high performance modes, then power consumption is reduced or performance is improved, but switching artefacts are generated during mode transitions
Solution Approach 1:
The repeater serves as an intermediary that smooths the transition between different clock rates. By buffering data and retransmitting it at the new clock rate, it prevents abrupt changes that would generate switching artefacts. This mediator ensures clean mode transitions while maintaining adaptability between power modes.
Solution Approach 2:
The system changes parameters (clock rate, filter coefficients) in a controlled manner during mode transitions. The clock divider and multiplexer adjust the internal clock rate gradually, and filter coefficients are updated to match the new operating mode, minimizing the generation of switching artefacts while maintaining versatility.
3Use of energy by stationary object
If traditional mode switching is implemented in digital microphones, then power consumption can be adjusted, but device complexity increases due to restart logic and clock management
Solution Approach 1:
The repeater performs multiple functions: it acts as a buffer, a clock rate converter, and an artefact reducer. The clock divider and multiplexer provide universal clock management that supports both low power and high performance modes with a single integrated approach, reducing overall device complexity while enabling power adjustment.
Solution Approach 2:
The system uses its existing components (ADC, repeater, digital filter) to handle mode transitions without requiring external control logic or additional restart mechanisms. The internal clock management system serves itself by automatically adjusting clock rates and coordinating component operation, simplifying the overall device architecture.
Data Source
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AI summary
A method of operating a microelectromechanical system (MEMS) includes, in a first operational mode, converting an analog output of the MEMS into a first internal data stream and a first external data stream having a first sampling rate; transitioning from the first operational mode to a second operation mode without restarting the MEMS; and in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and performing a sampling rate conversion of the second internal data stream to generate a second external data stream.