MEMS Microphone Integration via Through-Silicon Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The packaging of environmental microelectromechanical systems (MEMS) devices faces challenges due to parasitic capacitance generated by bonding wires and the high cost of forming individual packages using chip-level packaging, which degrades acoustic performance and increases costs.
Innovation Solution
The use of a wafer-level process that bonds application-specific integrated circuits (ASICs) to MEMS devices via through-silicon vias (TSVs) to reduce parasitic capacitance and form back volumes, incorporating an etch stop to prevent damage from vapor hydrofluoric acid during sacrificial oxide removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect MEMS devices to ASICs, then electrical connection is achieved, but parasitic capacitance increases degrading acoustic performance
Solution Approach 1:
The patent removes the bonding wire component from the system by implementing direct bond copper (DBC) technology. The DBC substrate integrates the copper trace directly into the substrate structure, eliminating the separate bonding wire that generates parasitic capacitance. This extraction of the harmful element (bonding wire) while maintaining the electrical connection function resolves the contradiction between achieving electrical connection and minimizing parasitic capacitance.
Solution Approach 2:
The DBC substrate acts as an intermediary component that provides both mechanical support and electrical connection. The copper trace embedded in the DBC substrate serves as a low-parasitic capacitance intermediary between the MEMS device and the ASIC, replacing the traditional bonding wire while maintaining electrical connectivity with improved acoustic performance.
2Reliability
If chip-level packaging is used to form individual packages, then complete MEMS systems are assembled, but production cost increases significantly
Solution Approach 1:
The patent merges multiple discrete components and packaging steps into a single integrated DBC substrate. The DBC substrate combines the function of the traditional packaging substrate, interconnect, and mechanical support structure into one component. This merging eliminates the need for separate bonding wire, individual packaging assembly, and multiple interconnection layers, thereby significantly reducing production cost while maintaining complete MEMS system functionality.
Solution Approach 2:
The DBC substrate performs multiple functions simultaneously: it provides mechanical support for the MEMS device, establishes electrical connections to the ASIC, serves as a heat sink, and acts as a structural platform for the complete MEMS system. This multi-functionality replaces what traditionally required multiple separate components and assembly steps, reducing production complexity and cost.
3Ease of manufacture
If vapor hydrofluoric acid is used to remove sacrificial oxide, then sacrificial oxide is eliminated, but IC device damage occurs
Solution Approach 1:
The patent introduces an etch stop layer as a protective intermediary between the sacrificial oxide and the IC device. This etch stop layer is positioned between the sacrificial oxide and the IC device, allowing the vapor hydrofluoric acid to selectively remove the sacrificial oxide while being blocked by the etch stop layer from reaching and damaging the IC device. The etch stop layer thus mediates the etching process to achieve oxide removal without harmful side effects.
Solution Approach 2:
The etch stop layer is deposited beforehand to provide protective cushioning for the IC device during the sacrificial oxide removal process. This pre-positioned protective layer anticipates the potential damage from vapor hydrofluoric acid and prevents it in advance, allowing the etching process to proceed safely without risking IC device integrity.
Data Source
AI summary
A microelectromechanical systems (MEMS) package includes a MEMS device and an integrated circuit (IC) device connected by a through silicon via (TSV). A conductive MEMS structure is arranged in a dielectric layer and includes a membrane region extending across a first volume arranged in the dielectric layer. A first substrate is bonded to a second substrate through the dielectric layer, where the MEMS device includes the second substrate. The TSV extends through the second substrate to electrically couple the MEMS device to the IC device. A third substrate is bonded to the second substrate to define a second volume between the second substrate and the third substrate, where the IC device includes the first or third substrate. A method for manufacturing the MEMS package is also provided.