High-Density MEMS Micro-Mirror Matrix With Under-Mirror Trace Routing
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Solution Overview
Problem
The challenge in constructing optical cross-connect systems is the limited space for MEMS actuators and signal traces due to the need for high-density mirror arrays with increased channels and tilting angles, leading to issues like decreased drive force and interference between channels, while also requiring a reduction in system footprint.
Innovation Solution
A high-density matrix of MEMS micro-mirrors is designed with two degrees of freedom, using movable electrostatic comb drives on separate device layers, insulated by air and sealed with inert gas, and connected via trench refill techniques, with traces that fan out to chip edges for increased channel count and reduced chip cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of mirrors on the MEMS mirror matrix is increased to increase channels, then the channel count is improved, but the silicon area for MEMS actuators and traces is reduced
Solution Approach 1:
The patent introduces a third device layer sandwiched between two insulating layers to route high voltage traces. This vertical dimensionality change allows traces to pass underneath mirrors in the Z-direction, enabling traces to reach chip edges without occupying additional planar silicon area, thus resolving the contradiction between increasing channel count and maintaining sufficient silicon area for actuators and traces.
Solution Approach 2:
The patent nests the third device layer containing traces within the vertical stack of the MEMS mirror structure. The traces are embedded in the third device layer which is positioned between the mirror array and the substrate, allowing trace routing to be nested within the existing device footprint without requiring additional lateral space.
2Quantity of substance
If the maximum tilting angle of each mirror is increased to increase channels, then the channel count is improved, but the drive force decreases
Solution Approach 1:
The patent positions the high voltage traces in a third device layer underneath the mirrors, which enhances the electrical field coupling between the traces and the movable comb drives. This spatial arrangement in the vertical dimension improves the electrostatic drive force available for achieving larger mirror tilting angles without sacrificing drive force.
3Quantity of substance
If the number of mirrors is increased to increase channels, then the channel count is improved, but drive interference between channels increases
Solution Approach 1:
The patent routes high voltage traces through a third device layer positioned underneath the mirror array, which spatially separates the traces from the movable comb drives in the vertical dimension. This separation reduces parasitic capacitance and electrical interference between adjacent channels, allowing for higher channel counts without significant drive interference.
4Area of stationary object
If the system footprint is reduced to decrease chip size, then the chip size is reduced, but the silicon area for MEMS actuators and traces is limited
Solution Approach 1:
The patent utilizes a third device layer in the vertical dimension to route high voltage traces underneath the mirror array. This allows trace routing to occur in the Z-direction rather than requiring additional lateral silicon area, enabling chip size reduction while maintaining sufficient space for both MEMS actuators and trace routing.
Solution Approach 2:
The patent segments the device into multiple functional layers: the first device layer for mirrors, the second device layer for stationary comb drives, and the third device layer for high voltage traces. This segmentation allows each layer to be optimized independently, with traces confined to the third layer to minimize their footprint on the silicon surface while maintaining electrical functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances breakdown voltage threshold, minimizes interference, and allows for scalable, cost-effective optical cross-connect systems with improved reliability and reduced chip size.
Implementation Method 1
pivoting mirrors with movable MEMS electrostatic comb drive
Implementation Method 2
The high voltage compatible silicon trace is insulated by air and sealed hermetically with low pressure inert gas to enhance breakdown voltage threshold
Data Source
AI summary
A mirror array apparatus may include a mirror array including a first mirror and a second mirror; a drive array including a first drive configured to drive the first mirror and a second drive configured to drive the second mirror; and a trace layer including a first trace electrically coupled to the first drive and a second trace electrically coupled to the second drive. The mirror array may be disposed above the trace layer, and at least portion of the first trace may overlap the second mirror and passes below the second mirror.